(no commit message)

[libreriscv.git] / cole.mdwn

diff --git a/cole.mdwn b/cole.mdwn
index 8a35b67d4190b691cb4401bf534a6ead4ce7f4ba..23349e1441f0974a4c8e4994466115a6a86daf30 100644 (file)
--- a/cole.mdwn
+++ b/cole.mdwn
@@ -11,7 +11,6 @@ move things along from one stage to the next
 ## Currently working on
 
 - Reach out to lu_zero of Gentoo about SV POWER binutils
-- <https://bugs.libre-soc.org/show_bug.cgi?id=383> Complete first functional POWER9 Core
 - <https://bugs.libre-soc.org/show_bug.cgi?id=486> Script and document the setup and installation of microwatt dependency on the wiki-HDL_workflow page 
 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
   - shared with lkcl
@@ -43,14 +42,17 @@ move things along from one stage to the next
 
 ## Completed but not yet submitted
 
+## Submitted for NLNet RFP
+
+submitted but not confirmed paid:
+
+## Paid
+
+# wishbone 2019-10-043 1-OCT-2020
+
 - <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG
   - EUR 150
 
-- Coriolis2 documentation and setup scripts, (documentation budget, EUR 200)
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=291>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=320>
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=404> Adding nmigen-soc as a dependency needs documentation updated
   - EUR 100
 
@@ -63,11 +65,9 @@ move things along from one stage to the next
 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> Virtual Regfile port
   - EUR 200. shared, lkcl (50%, EUR 100), cole (50%, EUR 100)
 
+# coriolis2 2019-10-029 1-OCT-2020
 
-## Submitted for NLNet RFP
-
-submitted but not confirmed paid:
-
-### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
-
-## Paid
+- Coriolis2 documentation and setup scripts, (documentation budget, EUR 200)
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=291>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=320>