(no commit message)

[libreriscv.git] / cole.mdwn

diff --git a/cole.mdwn b/cole.mdwn
index 1dc777623a448054badcef78d048e1d1b82227ff..23349e1441f0974a4c8e4994466115a6a86daf30 100644 (file)
--- a/cole.mdwn
+++ b/cole.mdwn
@@ -10,37 +10,64 @@ move things along from one stage to the next
 
 ## Currently working on
 
-- Recruiting more engineers to the project <https://bugs.libre-soc.org/show_bug.cgi?id=375> <https://bugs.libre-soc.org/show_bug.cgi?id=380> and make wiki pages(s) for this purpose <https://bugs.libre-soc.org/show_bug.cgi?id=379>
+- Reach out to lu_zero of Gentoo about SV POWER binutils
+- <https://bugs.libre-soc.org/show_bug.cgi?id=486> Script and document the setup and installation of microwatt dependency on the wiki-HDL_workflow page 
+- <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=484> Write VHDL to expose CR and XER from Microwatt so single-stepping is possible
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=485> Create I-Cache from microwatt icache.vhdl
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=469> Create D-cache from microwatt dcache.vhdl
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create MMU from microwatt mmu.vhdl
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=375> Recruiting more engineers to the project
+- <https://bugs.libre-soc.org/show_bug.cgi?id=380> First round of recruitment attempts
+- <https://bugs.libre-soc.org/show_bug.cgi?id=379> Create wiki page for recruitment emails to point to
+- <https://bugs.libre-soc.org/show_bug.cgi?id=388> bpermd tutorial 
+- <https://bugs.libre-soc.org/show_bug.cgi?id=389> Create bug report for each diagram to be converted to SVG 
+- <https://bugs.libre-soc.org/show_bug.cgi?id=394> Contact 'BlackParrot' RV64GC Multicore SoC devs
+- <https://bugs.libre-soc.org/show_bug.cgi?id=442> Convert comp_unit_req_rel diagram to SVG
 
-- Bperm tutorial <https://bugs.libre-soc.org/show_bug.cgi?id=388>
+## List of things that need more fleshed out bug reports:
 
-- Create a bug report for each diagram to be converted to SVG <https://bugs.libre-soc.org/show_bug.cgi?id=389>
+- Scoreboard documentation
+  - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
 
-- Reach out to developers of 'BlackParrot' RV64GC Multicore SoC <https://bugs.libre-soc.org/show_bug.cgi?id=394>
 
-- Convert comp_unit_req_rel diagram to SVG <https://bugs.libre-soc.org/show_bug.cgi?id=442>
+- LDST documentation
+  - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
 
-## List of things that need more fleshed out bug reports:
 
-* Scoreboard documentation (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>)
+## Completed but not yet submitted
 
-* LDST documentation (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>)
+## Submitted for NLNet RFP
 
-## Completed but not yet submitted
+submitted but not confirmed paid:
 
-- Convert hand-drawn 180nm Test ASIC's Memory Layout diagram into editable SVG <https://bugs.libre-soc.org/show_bug.cgi?id=401>
+## Paid
 
-- Coriolis2 documentation and setup scripts
-  <https://bugs.libre-soc.org/show_bug.cgi?id=291>
-  <https://bugs.libre-soc.org/show_bug.cgi?id=178>
-  <https://bugs.libre-soc.org/show_bug.cgi?id=320>
-  <https://bugs.libre-soc.org/show_bug.cgi?id=404>
-  <https://bugs.libre-soc.org/show_bug.cgi?id=138> 
+# wishbone 2019-10-043 1-OCT-2020
 
-## Submitted for NLNet RFP
+- <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG
+  - EUR 150
 
-submitted but not confirmed paid:
+- <https://bugs.libre-soc.org/show_bug.cgi?id=404> Adding nmigen-soc as a dependency needs documentation updated
+  - EUR 100
 
-### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
+- <https://bugs.libre-soc.org/show_bug.cgi?id=472> Tutorial and dev page needed for mesa driver 
+  - EUR 100
 
-## Paid
+- <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe discussion
+  - EUR 500. shared. lkcl (60%, EUR 300), cole (20%, EUR 100), samuel (20%, EUR 100)
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=351> Virtual Regfile port
+  - EUR 200. shared, lkcl (50%, EUR 100), cole (50%, EUR 100)
+
+# coriolis2 2019-10-029 1-OCT-2020
+
+- Coriolis2 documentation and setup scripts, (documentation budget, EUR 200)
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=291>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=320>