(no commit message)

[libreriscv.git] / cole.mdwn

diff --git a/cole.mdwn b/cole.mdwn
index 1eceb73926fee3b6825fe0f673e6c98cd2d2d5bb..5026a7371d92ebb95112f248226c35e7b6842c05 100644 (file)
--- a/cole.mdwn
+++ b/cole.mdwn
@@ -10,34 +10,58 @@ move things along from one stage to the next
 
 ## Currently working on
 
+- Reach out to lu_zero of Gentoo about SV POWER binutils
+- <https://bugs.libre-soc.org/show_bug.cgi?id=383> Complete first functional POWER9 Core
+- <https://bugs.libre-soc.org/show_bug.cgi?id=486> Script and document the setup and installation of microwatt dependency on the wiki-HDL_workflow page 
+- <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=484> Write VHDL to expose CR and XER from Microwatt so single-stepping is possible
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=485> Create I-Cache from microwatt icache.vhdl
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=469> Create D-cache from microwatt dcache.vhdl
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create MMU from microwatt mmu.vhdl
+  - shared with lkcl
 - <https://bugs.libre-soc.org/show_bug.cgi?id=375> Recruiting more engineers to the project
-- <https://bugs.libre-soc.org/show_bug.cgi?id=380> First round of recruitment attempts on university and technical mailing lists
+- <https://bugs.libre-soc.org/show_bug.cgi?id=380> First round of recruitment attempts
 - <https://bugs.libre-soc.org/show_bug.cgi?id=379> Create wiki page for recruitment emails to point to
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=388> bpermd tutorial 
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=389> Create bug report for each diagram to be converted to SVG 
-
-- <https://bugs.libre-soc.org/show_bug.cgi?id=394> Reach out to developers of 'BlackParrot' RV64GC Multicore SoC 
-
+- <https://bugs.libre-soc.org/show_bug.cgi?id=394> Contact 'BlackParrot' RV64GC Multicore SoC devs
 - <https://bugs.libre-soc.org/show_bug.cgi?id=442> Convert comp_unit_req_rel diagram to SVG
 
 ## List of things that need more fleshed out bug reports:
 
-* Scoreboard documentation (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>)
+- Scoreboard documentation
+  - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
+
+
+- LDST documentation
+  - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
 
-* LDST documentation (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>)
 
 ## Completed but not yet submitted
 
 - <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG 
 
-- Coriolis2 documentation and setup scripts
+- Coriolis2 documentation and setup scripts, (documentation budget, EUR 200)
   - <https://bugs.libre-soc.org/show_bug.cgi?id=291>
   - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
   - <https://bugs.libre-soc.org/show_bug.cgi?id=320>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=404>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=138> 
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=404> Adding nmigen-soc as a dependency needs documentation updated
+  - EUR 100
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=472> Tutorial and dev page needed for mesa driver 
+  - EUR 100
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe discussion
+  - EUR 500. shared. lkcl (60%, EUR 300), cole (20%, EUR 100), samuel (20%, EUR 100)
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=351> Virtual Regfile port
+  - EUR 200. shared, lkcl (50%, EUR 100), cole (50%, EUR 100)
+
 
 ## Submitted for NLNet RFP