update 22nm page

[libreriscv.git] / cole.mdwn

diff --git a/cole.mdwn b/cole.mdwn
index 23349e1441f0974a4c8e4994466115a6a86daf30..5dcf53a71a35bbcbbc78ad6305f6ec78d73f6883 100644 (file)
--- a/cole.mdwn
+++ b/cole.mdwn
@@ -42,13 +42,21 @@ move things along from one stage to the next
 
 ## Completed but not yet submitted
 
+- <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI JTAG TAP needed
+  - EUR 150
+
 ## Submitted for NLNet RFP
 
 submitted but not confirmed paid:
 
 ## Paid
 
-# wishbone 2019-10-043 1-OCT-2020
+### MOU coriolis2 2019-10-029, received payment on 2020-DEC-20
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=178> Coriolis2 tutorial
+  - EUR 500
+
+### MOU wishbone 2019-10-043, received payment on 2020-OCT-01
 
 - <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG
   - EUR 150
@@ -65,7 +73,7 @@ submitted but not confirmed paid:
 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> Virtual Regfile port
   - EUR 200. shared, lkcl (50%, EUR 100), cole (50%, EUR 100)
 
-# coriolis2 2019-10-029 1-OCT-2020
+### MOU coriolis2 2019-10-029, received payment on 2020-OCT-01
 
 - Coriolis2 documentation and setup scripts, (documentation budget, EUR 200)
   - <https://bugs.libre-soc.org/show_bug.cgi?id=291>