add rust users discussion

[libreriscv.git] / cole.mdwn

diff --git a/cole.mdwn b/cole.mdwn
index ec98359e826eb66d1bff32940de57e3e7cb8ec9d..9e90ed46b97a2a9bdd8aa53b81ed2757430b52fc 100644 (file)
--- a/cole.mdwn
+++ b/cole.mdwn
@@ -11,8 +11,18 @@ move things along from one stage to the next
 ## Currently working on
 
 - Reach out to lu_zero of Gentoo about SV POWER binutils
+- <https://bugs.libre-soc.org/show_bug.cgi?id=383> Complete first functional POWER9 Core
+- <https://bugs.libre-soc.org/show_bug.cgi?id=486> Script and document the setup and installation of microwatt dependency on the wiki-HDL_workflow page 
+- <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=484> Write VHDL to expose CR and XER from Microwatt so single-stepping is possible
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=485> Create I-Cache from microwatt icache.vhdl
+  - shared with lkcl
 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> Create D-cache from microwatt dcache.vhdl
+  - shared with lkcl
 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create MMU from microwatt mmu.vhdl
+  - shared with lkcl
 - <https://bugs.libre-soc.org/show_bug.cgi?id=375> Recruiting more engineers to the project
 - <https://bugs.libre-soc.org/show_bug.cgi?id=380> First round of recruitment attempts
 - <https://bugs.libre-soc.org/show_bug.cgi?id=379> Create wiki page for recruitment emails to point to
@@ -20,7 +30,6 @@ move things along from one stage to the next
 - <https://bugs.libre-soc.org/show_bug.cgi?id=389> Create bug report for each diagram to be converted to SVG 
 - <https://bugs.libre-soc.org/show_bug.cgi?id=394> Contact 'BlackParrot' RV64GC Multicore SoC devs
 - <https://bugs.libre-soc.org/show_bug.cgi?id=442> Convert comp_unit_req_rel diagram to SVG
-- <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL Pipeline unit tests
 
 ## List of things that need more fleshed out bug reports:
 
@@ -34,23 +43,29 @@ move things along from one stage to the next
 
 ## Completed but not yet submitted
 
-- <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG 
+## Submitted for NLNet RFP
+
+submitted but not confirmed paid:
 
-- Coriolis2 documentation and setup scripts
+- <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG
+  - EUR 150
+
+- Coriolis2 documentation and setup scripts, (documentation budget, EUR 200)
   - <https://bugs.libre-soc.org/show_bug.cgi?id=291>
   - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
   - <https://bugs.libre-soc.org/show_bug.cgi?id=320>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=404>
 
-- Tutorial and dev page needed for mesa driver 
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=472>
+- <https://bugs.libre-soc.org/show_bug.cgi?id=404> Adding nmigen-soc as a dependency needs documentation updated
+  - EUR 100
 
-- TRAP pipeline discussion
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=325>
+- <https://bugs.libre-soc.org/show_bug.cgi?id=472> Tutorial and dev page needed for mesa driver 
+  - EUR 100
 
-## Submitted for NLNet RFP
+- <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe discussion
+  - EUR 500. shared. lkcl (60%, EUR 300), cole (20%, EUR 100), samuel (20%, EUR 100)
 
-submitted but not confirmed paid:
+- <https://bugs.libre-soc.org/show_bug.cgi?id=351> Virtual Regfile port
+  - EUR 200. shared, lkcl (50%, EUR 100), cole (50%, EUR 100)
 
 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}