whoops one extra bit on the overflow test in mullw/mulld

[libreriscv.git] / cole.mdwn

diff --git a/cole.mdwn b/cole.mdwn
index e0deb1f421705c812605e78cf5713cd472b76c53..c7b97e30a077a90d2a793af0e64d18cdc067834a 100644 (file)
--- a/cole.mdwn
+++ b/cole.mdwn
@@ -4,13 +4,21 @@
 
 * <https://bugs.libre-soc.org/show_bug.cgi?id=325>
 
+* Convert hand-drawn 180nm Test ASIC's Memory Layout diagram into editable SVG <https://bugs.libre-soc.org/show_bug.cgi?id=401> (see also [Bug #397](https://bugs.libre-soc.org/show_bug.cgi?id=397))
+
 List of things that need more fleshed out bug reports:
 
-* Convert hand-drawn 180nm Test ASIC's Memory Layout diagram into editable SVG
+
+* Memory bus/L1/L2 Cache documentation <https://bugs.libre-soc.org/show_bug.cgi?id=397>
+
 * Bperm tutorial
-* Bugseverywhere
-* Competition to LS: Skywater 130nm production-ready PDK gets opensourced (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008254.html)
-* Memory bus/L1/L2 Cache documentation  (bug #397)
-* Scoreboard documentation (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html)
-* LDST documentation (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html)
-* Follow up with graphics engineers, esp ones Yehowshua has already reached out to (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008283.html)
+
+* Bugseverywhere, need specific bug report for discussing new bug tracker and migration (or also <https://github.com/MichaelMure/git-bug/blob/master/bug/bug.go>)
+
+* Competition to LS: Skywater 130nm production-ready PDK gets opensourced (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008254.html>)
+
+* Scoreboard documentation (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>)
+
+* LDST documentation (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>)
+
+* Follow up with graphics engineers, esp ones Yehowshua has already reached out to (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008283.html>)