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[libreriscv.git] / cole.mdwn

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 # Cole Poirier
 
-* [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=colepoirier%40gmail.com&emailassigned_to1=1&emailtype1=substring&resolution=---)
+* [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=colepoirier%40gmail.com&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)
+
+* <https://bugs.libre-soc.org/show_bug.cgi?id=325>
+
+* Convert hand-drawn 180nm Test ASIC's Memory Layout diagram into editable SVG <https://bugs.libre-soc.org/show_bug.cgi?id=401> (see also [Bug #397](https://bugs.libre-soc.org/show_bug.cgi?id=397))
+
+List of things that need more fleshed out bug reports:
+
+
+* Memory bus/L1/L2 Cache documentation <https://bugs.libre-soc.org/show_bug.cgi?id=397>
+
+* Bperm tutorial
+
+* Bugseverywhere, need specific bug report for discussing new bug tracker and migration (or also <https://github.com/MichaelMure/git-bug/blob/master/bug/bug.go>)
+
+* Competition to LS: Skywater 130nm production-ready PDK gets opensourced (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008254.html>)
+
+* Scoreboard documentation (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>)
+
+* LDST documentation (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>)
+
+* Follow up with graphics engineers, esp ones Yehowshua has already reached out to (<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008283.html>)