(no commit message)

[libreriscv.git] / cole.mdwn

diff --git a/cole.mdwn b/cole.mdwn
index 0786f8b8a839f30e7aed2ab154374414e00efdbd..f4eaf9cea22093a5a411d338270b4de018f16df5 100644 (file)
--- a/cole.mdwn
+++ b/cole.mdwn
@@ -10,6 +10,9 @@ move things along from one stage to the next
 
 ## Currently working on
 
+- Reach out to lu_zero of Gentoo about SV POWER binutils
+- <https://bugs.libre-soc.org/show_bug.cgi?id=469> Create D-cache from microwatt dcache.vhdl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create MMU from microwatt mmu.vhdl
 - <https://bugs.libre-soc.org/show_bug.cgi?id=375> Recruiting more engineers to the project
 - <https://bugs.libre-soc.org/show_bug.cgi?id=380> First round of recruitment attempts
 - <https://bugs.libre-soc.org/show_bug.cgi?id=379> Create wiki page for recruitment emails to point to
@@ -17,6 +20,7 @@ move things along from one stage to the next
 - <https://bugs.libre-soc.org/show_bug.cgi?id=389> Create bug report for each diagram to be converted to SVG 
 - <https://bugs.libre-soc.org/show_bug.cgi?id=394> Contact 'BlackParrot' RV64GC Multicore SoC devs
 - <https://bugs.libre-soc.org/show_bug.cgi?id=442> Convert comp_unit_req_rel diagram to SVG
+- <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL Pipeline unit tests
 
 ## List of things that need more fleshed out bug reports:
 
@@ -37,7 +41,10 @@ move things along from one stage to the next
   - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
   - <https://bugs.libre-soc.org/show_bug.cgi?id=320>
   - <https://bugs.libre-soc.org/show_bug.cgi?id=404>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=138> 
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=138>
+
+- TRAP pipeline discussion
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=138>
 
 ## Submitted for NLNet RFP