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[libreriscv.git] / cole.mdwn

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 # Cole Poirier
 
+Apprentice and assistant Project coordinator for Libre-SOC
+
 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=colepoirier%40gmail.com&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)
 
-* <https://bugs.libre-soc.org/show_bug.cgi?id=325>
+# Status tracking
+
+move things along from one stage to the next
+
+## Currently working on
+
+- Reach out to lu_zero of Gentoo about SV POWER binutils
+- <https://bugs.libre-soc.org/show_bug.cgi?id=469> Create D-cache from microwatt dcache.vhdl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create MMU from microwatt mmu.vhdl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=375> Recruiting more engineers to the project
+- <https://bugs.libre-soc.org/show_bug.cgi?id=380> First round of recruitment attempts
+- <https://bugs.libre-soc.org/show_bug.cgi?id=379> Create wiki page for recruitment emails to point to
+- <https://bugs.libre-soc.org/show_bug.cgi?id=388> bpermd tutorial 
+- <https://bugs.libre-soc.org/show_bug.cgi?id=389> Create bug report for each diagram to be converted to SVG 
+- <https://bugs.libre-soc.org/show_bug.cgi?id=394> Contact 'BlackParrot' RV64GC Multicore SoC devs
+- <https://bugs.libre-soc.org/show_bug.cgi?id=442> Convert comp_unit_req_rel diagram to SVG
+- <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL Pipeline unit tests
+
+## List of things that need more fleshed out bug reports:
+
+- Scoreboard documentation
+  - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
+
+
+- LDST documentation
+  - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
+
+
+## Completed but not yet submitted
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG 
+
+- Coriolis2 documentation and setup scripts
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=291>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=320>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=404>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=138>
+
+- TRAP pipeline discussion
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=138>
+
+## Submitted for NLNet RFP
+
+submitted but not confirmed paid:
 
-List of things that need more fleshed out bug reports:
+### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 
-* Convert hand-drawn 180nm Test ASIC's Memory Layout diagram into editable SVG
-* Bperm tutorial
-* Bugseverywhere (or also https://github.com/MichaelMure/git-bug/blob/master/bug/bug.go)
-* Competition to LS: Skywater 130nm production-ready PDK gets opensourced (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008254.html)
-* Memory bus/L1/L2 Cache documentation  (bug #397)
-* Scoreboard documentation (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html)
-* LDST documentation (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html)
-* Follow up with graphics engineers, esp ones Yehowshua has already reached out to (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008283.html)
+## Paid