constant SPR_SPRG3U : spr_num_t := 259;
constant SPR_HSPRG0 : spr_num_t := 304;
constant SPR_HSPRG1 : spr_num_t := 305;
- constant SPR_PGTBL0 : spr_num_t := 720;
+ constant SPR_PID : spr_num_t := 48;
+ constant SPR_PRTBL : spr_num_t := 720;
-- GPR indices in the register file (GPR only)
subtype gpr_index_t is std_ulogic_vector(4 downto 0);
type Fetch1ToIcacheType is record
req: std_ulogic;
+ virt_mode : std_ulogic;
+ priv_mode : std_ulogic;
stop_mark: std_ulogic;
nia: std_ulogic_vector(63 downto 0);
end record;
- type IcacheToFetch2Type is record
+ type IcacheToDecode1Type is record
valid: std_ulogic;
stop_mark: std_ulogic;
+ fetch_failed: std_ulogic;
nia: std_ulogic_vector(63 downto 0);
insn: std_ulogic_vector(31 downto 0);
end record;
- type Fetch2ToDecode1Type is record
- valid: std_ulogic;
- stop_mark : std_ulogic;
- nia: std_ulogic_vector(63 downto 0);
- insn: std_ulogic_vector(31 downto 0);
- end record;
- constant Fetch2ToDecode1Init : Fetch2ToDecode1Type := (valid => '0', stop_mark => '0', others => (others => '0'));
-
type Decode1ToDecode2Type is record
valid: std_ulogic;
stop_mark : std_ulogic;
ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
decode: decode_rom_t;
end record;
- constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', stop_mark => '0', decode => decode_rom_init, others => (others => '0'));
+ constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'), ispr1 => (others => '0'), ispr2 => (others => '0'), decode => decode_rom_init);
type Decode2ToExecute1Type is record
valid: std_ulogic;
lr => '0', rc => '0', oe => '0', invert_a => '0',
invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0',
- byte_reverse => '0', sign_extend => '0', update => '0', others => (others => '0'));
+ byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'), read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'), cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'), others => (others => '0'));
type Execute1ToMultiplyType is record
valid: std_ulogic;
type Execute1ToFetch1Type is record
redirect: std_ulogic;
+ virt_mode: std_ulogic;
+ priv_mode: std_ulogic;
redirect_nia: std_ulogic_vector(63 downto 0);
end record;
- constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', others => (others => '0'));
+ constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
+ priv_mode => '0', others => (others => '0'));
type Execute1ToLoadstore1Type is record
valid : std_ulogic;
op : insn_type_t; -- what ld/st or m[tf]spr or TLB op to do
+ nia : std_ulogic_vector(63 downto 0);
+ insn : std_ulogic_vector(31 downto 0);
addr1 : std_ulogic_vector(63 downto 0);
addr2 : std_ulogic_vector(63 downto 0);
data : std_ulogic_vector(63 downto 0); -- data to write, unused for read
rc : std_ulogic; -- set for stcx.
virt_mode : std_ulogic; -- do translation through TLB
priv_mode : std_ulogic; -- privileged mode (MSR[PR] = 0)
- spr_num : spr_num_t; -- SPR number for mfspr/mtspr
end record;
constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
sign_extend => '0', update => '0', xerc => xerc_init,
reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
- spr_num => 0, others => (others => '0'));
+ nia => (others => '0'), insn => (others => '0'),
+ addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'), length => (others => '0'),
+ others => (others => '0'));
type Loadstore1ToExecute1Type is record
exception : std_ulogic;
+ invalid : std_ulogic;
+ perm_error : std_ulogic;
+ rc_error : std_ulogic;
+ badtree : std_ulogic;
+ segment_fault : std_ulogic;
+ instr_fault : std_ulogic;
end record;
type Loadstore1ToDcacheType is record
data : std_ulogic_vector(63 downto 0);
store_done : std_ulogic;
error : std_ulogic;
- tlb_miss : std_ulogic;
- perm_error : std_ulogic;
- rc_error : std_ulogic;
+ cache_paradox : std_ulogic;
end record;
type Loadstore1ToMmuType is record
valid : std_ulogic;
tlbie : std_ulogic;
+ slbia : std_ulogic;
mtspr : std_ulogic;
- sprn : std_ulogic_vector(3 downto 0);
+ iside : std_ulogic;
+ load : std_ulogic;
+ priv : std_ulogic;
+ sprn : std_ulogic_vector(9 downto 0);
addr : std_ulogic_vector(63 downto 0);
rs : std_ulogic_vector(63 downto 0);
end record;
type MmuToLoadstore1Type is record
- done : std_ulogic;
- invalid : std_ulogic;
- badtree : std_ulogic;
- sprval : std_ulogic_vector(63 downto 0);
+ done : std_ulogic;
+ invalid : std_ulogic;
+ badtree : std_ulogic;
+ segerr : std_ulogic;
+ perm_error : std_ulogic;
+ rc_error : std_ulogic;
+ sprval : std_ulogic_vector(63 downto 0);
end record;
type MmuToDcacheType is record
valid : std_ulogic;
tlbie : std_ulogic;
+ doall : std_ulogic;
tlbld : std_ulogic;
addr : std_ulogic_vector(63 downto 0);
pte : std_ulogic_vector(63 downto 0);
data : std_ulogic_vector(63 downto 0);
end record;
+ type MmuToIcacheType is record
+ tlbld : std_ulogic;
+ tlbie : std_ulogic;
+ doall : std_ulogic;
+ addr : std_ulogic_vector(63 downto 0);
+ pte : std_ulogic_vector(63 downto 0);
+ end record;
+
type Loadstore1ToWritebackType is record
valid : std_ulogic;
write_enable: std_ulogic;
store_done : std_ulogic;
end record;
constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
- rc => '0', store_done => '0', others => (others => '0'));
+ rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
type Execute1ToWritebackType is record
valid: std_ulogic;
constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
write_cr_enable => '0', exc_write_enable => '0',
write_xerc_enable => '0', xerc => xerc_init,
- others => (others => '0'));
+ write_data => (others => '0'), write_cr_mask => (others => '0'),
+ write_cr_data => (others => '0'), write_reg => (others => '0'),
+ exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
type MultiplyToExecute1Type is record
valid: std_ulogic;
write_data : std_ulogic_vector(63 downto 0);
write_enable : std_ulogic;
end record;
- constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', others => (others => '0'));
+ constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
type WritebackToCrFileType is record
write_cr_enable : std_ulogic;
end record;
constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
write_xerc_data => xerc_init,
- others => (others => '0'));
-
- type XicsToExecute1Type is record
- irq : std_ulogic;
- end record;
+ write_cr_mask => (others => '0'),
+ write_cr_data => (others => '0'));
end common;
end;
function fast_spr_num(spr: spr_num_t) return gspr_index_t is
variable n : integer range 0 to 31;
+ -- tmp variable introduced as workaround for VCS compilation
+ -- simulation was failing with subtype constraint mismatch error
+ -- see GitHub PR #173
+ variable tmp : std_ulogic_vector(4 downto 0);
begin
case spr is
when SPR_LR =>
n := 0;
return "000000";
end case;
- return "1" & std_ulogic_vector(to_unsigned(n, 5));
+ tmp := std_ulogic_vector(to_unsigned(n, 5));
+ return "1" & tmp;
end;
function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
projects / microwatt.git / blobdiff