divider: Reduce delay in detecting 32-bit overflow

[microwatt.git] / common.vhdl

diff --git a/common.vhdl b/common.vhdl
index 399ab985ac2a8711f40f6522e9f225389a4ac36b..ae61342ff91bad39164d75069a0519b6bb26abdc 100644 (file)
--- a/common.vhdl
+++ b/common.vhdl
@@ -12,24 +12,35 @@ package common is
                carry: std_ulogic;
        end record;
 
-       type Fetch1ToFetch2Type is record
+       type Fetch1ToIcacheType is record
+               req: std_ulogic;
+               stop_mark: std_ulogic;
                nia: std_ulogic_vector(63 downto 0);
        end record;
 
+       type IcacheToFetch2Type is record
+               valid: std_ulogic;
+               stop_mark: std_ulogic;
+               nia: std_ulogic_vector(63 downto 0);
+               insn: std_ulogic_vector(31 downto 0);
+       end record;
+
        type Fetch2ToDecode1Type is record
                valid: std_ulogic;
+               stop_mark : std_ulogic;
                nia: std_ulogic_vector(63 downto 0);
                insn: std_ulogic_vector(31 downto 0);
        end record;
-       constant Fetch2ToDecode1Init : Fetch2ToDecode1Type := (valid => '0', others => (others => '0'));
+       constant Fetch2ToDecode1Init : Fetch2ToDecode1Type := (valid => '0', stop_mark => '0', others => (others => '0'));
 
        type Decode1ToDecode2Type is record
                valid: std_ulogic;
+               stop_mark : std_ulogic;
                nia: std_ulogic_vector(63 downto 0);
                insn: std_ulogic_vector(31 downto 0);
                decode: decode_rom_t;
        end record;
-       constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', decode => decode_rom_init, others => (others => '0'));
+       constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', stop_mark => '0', decode => decode_rom_init, others => (others => '0'));
 
        type Decode2ToExecute1Type is record
                valid: std_ulogic;
@@ -40,18 +51,24 @@ package common is
                read_reg2: std_ulogic_vector(4 downto 0);
                read_data1: std_ulogic_vector(63 downto 0);
                read_data2: std_ulogic_vector(63 downto 0);
-               const1: std_ulogic_vector(7 downto 0);
-               const2: std_ulogic_vector(5 downto 0);
-               const3: std_ulogic_vector(4 downto 0);
+               read_data3: std_ulogic_vector(63 downto 0);
                cr: std_ulogic_vector(31 downto 0);
                lr: std_ulogic;
                rc: std_ulogic;
-               input_carry: std_ulogic;
+                invert_a: std_ulogic;
+                invert_out: std_ulogic;
+               input_carry: carry_in_t;
                output_carry: std_ulogic;
                input_cr: std_ulogic;
                output_cr: std_ulogic;
+               is_32bit: std_ulogic;
+               is_signed: std_ulogic;
+                insn: std_ulogic_vector(31 downto 0);
        end record;
-       constant Decode2ToExecute1Init : Decode2ToExecute1Type := (valid => '0', insn_type => OP_ILLEGAL, lr => '0', rc => '0', input_carry => '0', output_carry => '0', input_cr => '0', output_cr => '0', others => (others => '0'));
+       constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
+               (valid => '0', insn_type => OP_ILLEGAL, lr => '0', rc => '0', invert_a => '0',
+                invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
+                is_32bit => '0', is_signed => '0', others => (others => '0'));
 
        type Decode2ToMultiplyType is record
                valid: std_ulogic;
@@ -63,6 +80,19 @@ package common is
        end record;
        constant Decode2ToMultiplyInit : Decode2ToMultiplyType := (valid => '0', insn_type => OP_ILLEGAL, rc => '0', others => (others => '0'));
 
+        type Decode2ToDividerType is record
+                valid: std_ulogic;
+               write_reg: std_ulogic_vector(4 downto 0);
+                dividend: std_ulogic_vector(63 downto 0);
+                divisor: std_ulogic_vector(63 downto 0);
+                is_signed: std_ulogic;
+                is_32bit: std_ulogic;
+                is_extended: std_ulogic;
+                is_modulus: std_ulogic;
+                rc: std_ulogic;
+        end record;
+        constant Decode2ToDividerInit: Decode2ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0', is_extended => '0', is_modulus => '0', rc => '0', others => (others => '0'));
+
        type Decode2ToRegisterFileType is record
                read1_enable : std_ulogic;
                read1_reg : std_ulogic_vector(4 downto 0);
@@ -163,6 +193,18 @@ package common is
        end record;
        constant MultiplyToWritebackInit : MultiplyToWritebackType := (valid => '0', write_reg_enable => '0', write_cr_enable => '0', others => (others => '0'));
 
+       type DividerToWritebackType is record
+               valid: std_ulogic;
+
+               write_reg_enable : std_ulogic;
+               write_reg_nr: std_ulogic_vector(4 downto 0);
+               write_reg_data: std_ulogic_vector(63 downto 0);
+               write_cr_enable: std_ulogic;
+               write_cr_mask: std_ulogic_vector(7 downto 0);
+               write_cr_data: std_ulogic_vector(31 downto 0);
+       end record;
+       constant DividerToWritebackInit : DividerToWritebackType := (valid => '0', write_reg_enable => '0', write_cr_enable => '0', others => (others => '0'));
+
        type WritebackToRegisterFileType is record
                write_reg : std_ulogic_vector(4 downto 0);
                write_data : std_ulogic_vector(63 downto 0);
@@ -176,10 +218,6 @@ package common is
                write_cr_data : std_ulogic_vector(31 downto 0);
        end record;
        constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', others => (others => '0'));
-
-       -- Would prefer not to expose this outside the register file, but ghdl
-       -- doesn't support external names
-       type regfile is array(0 to 32) of std_ulogic_vector(63 downto 0);
 end common;
 
 package body common is