* <https://ics21.github.io/>
* <https://www.timeanddate.com/worldclock/meetingtime.html?day=14&month=6&year=2021&p1=%20141&p2=236&p3=1234&p4=250&p5=24&p6=224&iv=0>
* <https://meep-project.eu/events/ics-2021>
+* <https://www.youtube.com/channel/UCmkFegzIFCU-q33B7DAKfFQ>
+* <https://www.youtube.com/watch?v=LOCPTh4gVyc&t=3650s>
# Luke Leighton bio
Luke Kenneth Casson Leighton specialises in Libre Ethical Technology.
-He has been using and programming computers continuously for 44 years,
-has a BEng (Hons), ACGI, in Theory of Computing from Imperial College,
-and recently put that education to good use in the form of the Libre-SOC
+He has been using, programming and reverse-engineering computing
+devices continuously for 44 years, has a BEng (Hons), ACGI, in
+Theory of Computing from Imperial College, and recently put that
+education to good use in the form of the Libre-SOC
Project: an entirely Libre-Licensed 3D Hybrid CPU-VPU-GPU based on
OpenPOWER. He writes poetry and has been developing a HEP Physics theory
for the past 36 years in his spare time.
-# SVP64 Abstract
+## SVP64 Abstract
The OpenPOWER ISA has a strong multi-decades pedigree in Supercomputing:
Matrix Multiply, 128-bit SIMD, BCD, Decimal Floating-point have been part
This talk will go through the development process of SVP64 and explain
some of the innovative Vectorisation concepts that have never been seen
before in any commercial or academic Vector ISA, including
-Twin-Predication and "Post-result" predication, and how these will
-benefit Supercomputing performance and decrease power consumption,
-by reducing I-Cache usage.
+Twin-Predication and Condition Register "Post-result" predication,
+and how these will benefit Supercomputing performance and decrease
+power consumption, most notably by reducing program size and
+thus I-Cache usage whilst still maintaining high data throughput.
+
+## Comprehensive life-cycle of mixed testing: HDL to gates
+
+The Libre-SOC Project is developed by Software Engineers with a Hardware
+background: in particular, Software Engineers with decades of experience
+in the Libre / Open software ecosystem. There is a huge difference.
+
+Software Engineers have it drummed into them from either training or
+bitter experience that unit tests are critical at every level. Whilst
+the Validation Process for an ASIC goes through a rigorous process
+in the Synthesis Tools to ensure its correctness at every step, the
+actual HDL itself, shockingly, is typically put together in its entirety.
+Only on completion are high-level (binary) unit tests run. Errors
+in a low-level subsystem thus become extremely hard to find.
+
+In addition to that, as a Libre Project, we have had to use Libre
+VLSI tools. These are in active development and have not - yet -
+been used to develop ASICs beyond 130nm or over 1,000,000 gates.
+Our ASIC toolchain and HDL verification procedures are therefore
+functional but a little different from Industry-standard (proprietary)
+norm.
+
+This talk will therefore show, by example, how we went from low-level
+modules (with unit tests and Formal Correctness Proofs), to pipelines
+(with unit tests and Formal Correctness Proofs), to a functional Core
+(with several thousand unit tests), right the way to ASIC layout,
+from which the Netlist was extracted and then co-simulated with cocotb.
+At each and every stage - both pre and post layout and on FPGA - it
+has been possible to run the exact same JTAG Boundary Scan and basic
+startup procedure.
+
+
+# Jean-Paul Chaput bio
+
+Jean-Paul Chaput holds a Master Degree in MicroElectronics and Software
+Engineering. He joined the LIP6 laboratory within Sorbonne Université or SU
+(formerly UPMC) in 2000. Currently he is a Research Engineer in the Analog and
+Mixed Signal Team at LIP6. His main focus is on physical level design
+software. He is a key contributor in developing and maintaining the
+Alliance/Coriolis VLSI CAD projects for CMOS technologies. In particular he
+contributed in developing the routers of both Alliance/Coriolis and the whole
+Coriolis toolchain infrastructure. He his now a key contributor in extending
+Alliance/Coriolis to the Analog Mixed-Signal integration for nanometric CMOS
+technologies.
+
+## How to make an ASIC
+
+* <https://youtu.be/EkCD6srelYo?t=99>
+
+## ICS 2021 Abstract
+
+Starting in 1990, Sorbonne Université-CNRS/LIP6 developed Alliance, a complete
+VLSI CAD toolchain released under GPL. In this spirit, we are assembling an
+upgraded design flow for ASICs based on FOSS tools like GHDL & Yosys for
+logical synthesis and Coriolis2 for physical design. We will present the flow
+with a focus on the Coriolis2 part and the LibreSOC first prototype. This
+should be an important milestone toward the creation of an open hardware
+community.
projects / libreriscv.git / blobdiff