# ICS2022
-27 June 2021
+27 June 2022
-* <https://ics21.github.io/>
-* <https://www.timeanddate.com/worldclock/meetingtime.html?day=14&month=6&year=2021&p1=%20141&p2=236&p3=1234&p4=250&p5=24&p6=224&iv=0>
-* <https://meep-project.eu/events/ics-2021>
-* <https://www.youtube.com/channel/UCmkFegzIFCU-q33B7DAKfFQ>
-* <https://www.youtube.com/watch?v=LOCPTh4gVyc&t=3650s>
+* <https://ics2022.github.io/>
+* <https://meep-project.eu/form/workshop-on-risc-v-and-openpower>
+* <https://meep-project.eu/events/3rd-workshop-risc-v-and-openpower-hpc>
+* <https://libre-soc.org/openpower/sv/SimpleV_rationale/>
# Luke Leighton bio
Snitch also led the way, bringing back Auto-increment Load/Store from
the CISC era, but hidden behind Tagged Registers connected to
Coherent FIFOs leading indirectly to main Memory. Where both Snitch
-and Extra-V used limited variants of Deterministic Loops as proof-of-concept
-of the overall , ZOLC is
-a much more extensive and well-defined
+and Extra-V used limited variants of Deterministic Loops as
+proof-of-concept to support their overall research, with only rudimentary
+processing capability,
+ZOLC is a much more deeply extensive and well-defined Deterministic Loop
+Control system that can fit directly on top of a standard ISA.
SVP64 takes the Zero-Overhead Loop concept firmly into Supercomputing
Vector Processing territory, currently limited to the register file.
pioneering techniques, combining SVP64 and ZOLC, and leveraging OpenCAPI,
on top of the OpenPOWER ISA, to create High-performance Coherent
Distributed Computing with the potential to run large-scale Parallel
-Compute tasks at 100% sustained throughput, using assembly intrinsics at
+Compute tasks at 100% sustained throughput whilst also bringing the potential
+of Snitch's 85% power-consumption-reduction to bear, using assembly intrinsics at
in a normal everyday ubiquitous Software environment: no specialist
parallel programming languages or special compilers needed.
projects / libreriscv.git / blobdiff