* <http://sfscon.it/> - Roberto PPC64 Notebook
* <https://www.sfscon.it/talks/202x-open-hardware-concrete-approach/>
+* [[conferences/sfscon2020]]
-## Why a Libre 3D CPU / GPU / VPU?
-
-* Study of SoCs (Allwinner, Rockchip, NXP) shows none are fully Libre
- - Either GPU driver firmware is proprietary, or VPU firmware, or bootloader
-* This causes customer product development issues
- - https://tinyurl.com/valve-steam-intel
-* Businesses are waking up to lack of transparency
- - Intel Management Engine (spying backdoor co-processor)
- - Spectre, Meltdown, CSME (Chain-of-Trust) issues
-* Solution: full transparency. All source available for everything.
-
-## How is LibreSOC being developed?
-
-* Using Libre (rather than "open") development practices
- - no "I'll release it when it's ready": all development is real-time public access
-* No NDAs, no hidden discussions
- - we can invite anyone (any expert) to help with review
- - free to ask for help anywhere in the world (comp.arch, stackexchange)
-* Using litex, nmigen, opencores HDL
- - heavily depending on python OO (not possible with VHDL or Verilog)
- - leap-frogging ahead by not reinventing the wheel
-
-## Why is it different from other SoCs?
-
-* LibreSOC is a hybrid CPU-VPU-GPU architecture.
- - OpenPOWER ISA *itself* is extended to include 3D and Video instructions
- - (SIN, ATAN2, YUV2RGB, Texture Interpolation)
- - Only after approval of OpenPOWER Foundation!
- - Massively simplifies driver development and application debugging
-* Vectorisation is "Simple-V" (VSX not being implemented)
- - VSX is SIMD and is considered harmful
- - https://www.sigarch.org/simd-instructions-considered-harmful/
-* Developed in python HDL called "nmigen"
- - OO programming techniques can be used (not possible in VHDL/Verilog)
- - yosys converts nmigen to verilog for standard tools.
-
-## What is being developed? (Roadmap)
-
-* First simple core achieved in simulation Sep 2020
- - FPGA (ECP5) target followed shortly
-* First silicon tape-out 180nm deadline 2nd Dec 2020
- - sponsored by NLnet, with help from Chips4Makers Libre Cell Libraries
- - layout is entirely libre-licensed tools: coriolis2 from lip6.fr
-* Next chip is "SBC" style quad-core
- - similar spec to Allwinner A64, Rockchip RK3399
- - targets "Pi" boards, smartphones, tablets, Industrial IoT
-
-## Contact
-
-* Freenode IRC #libre-soc
-* Website https://libre-soc.org
- - mailing list, git repos, bugtracker etc.
+
+# FOSDEM 2021 OpenPOWER
+
+* <https://penta.fosdem.org/submission/FOSDEM21/events>
+* <https://lists.fosdem.org/pipermail/fosdem/2020q4/003123.html>
+* <https://fosdem.org/2021/schedule/tracks/>
+* <https://fosdem.org/2021/schedule/track/openpower/>
+* Stand <https://stands.fosdem.org/stands/the_libresoc_project__a_hybrid_3d_cpu_vpu_gpu/>
+* Main LibreSOC talk - done <https://www.youtube.com/watch?v=7rCeNzrCB_g>
+* nmigen-related tech - cancelled
+* SimpleV talk - done <https://www.youtube.com/watch?v=FS6tbfyb2VA>
+* Vulkan / Kazan - not submitted
+* other?
+
+# LinuxConf 2021
+
+* <https://lca2021.linux.org.au/schedule/presentation/78/>
+
+# Europython 2021
+
+march for CfP
+
+* <https://ep2021.europython.eu/faq/#nodes>
+
+# 3mdeb beer event
+
+* <https://live.evenea.com/3mdeb-vbeer>
projects / libreriscv.git / blobdiff