# XDC 2020
* <https://xdc2020.x.org/event/9/abstracts/>
-[[conferences/xdc2020]]
+* [[conferences/xdc2020]]
+* <https://ftp.libre-soc.org/xdc2020-libresoc-lkcl.pdf>
# OpenPOWER 2020
* <https://linuxfoundation.smapply.io/prog/openpower_na_2020/>
* <https://openpowerna2020.sched.com/>
* <https://openpowerna2020.sched.com/event/eDqa/the-libresoc-initiative-a-hybrid-cpuvpugpu-luke-leighton-libresoc?iframe=no&w=100%&sidebar=yes&bg=no>
+* <https://ftp.libre-soc.org/openpower_2020.pdf>
# SFSCON 2020, italy
* <http://sfscon.it/> - Roberto PPC64 Notebook
* <https://www.sfscon.it/talks/202x-open-hardware-concrete-approach/>
+* [[conferences/sfscon2020]]
-## Why a Libre 3D CPU / GPU / VPU?
-
-* Study of SoCs (Allwinner, Rockchip, NXP) shows none are fully Libre
- - Either GPU driver firmware is proprietary, or VPU firmware, or bootloader
-* This causes customer product development issues
- - https://tinyurl.com/valve-steam-intel
-* Businesses are waking up to lack of transparency
- - Intel Management Engine (spying backdoor co-processor)
- - Spectre, Meltdown, CSME (Chain-of-Trust) issues
-* Solution: full transparency. All source available for everything.
-
-## How is LibreSOC being developed?
-
-* Using Libre (rather than "open") development practices
- - no "I'll release it when it's ready": all development is real-time public access
-* No NDAs, no hidden discussions
- - we can invite anyone (any expert) to help with review
- - free to ask for help anywhere in the world (comp.arch, stackexchange)
-* Using litex, nmigen, opencores HDL
- - heavily depending on python OO (not possible with VHDL or Verilog)
- - leap-frogging ahead by not reinventing the wheel
- - yosys converts nmigen to verilog for standard tools.
-
-## Why is it different from other SoCs?
-
-* LibreSOC is a hybrid CPU-VPU-GPU architecture.
- - OpenPOWER ISA *itself* is extended to include 3D and Video instructions
- - (SIN, ATAN2, YUV2RGB, Texture Interpolation)
- - Only after approval of OpenPOWER Foundation!
- - There is no separate GPU or VPU: it really is the same core.
- - Massively simplifies driver development and application debugging
-* Vectorisation is "Simple-V" (VSX not being implemented)
- - VSX is SIMD and is considered harmful
- - https://www.sigarch.org/simd-instructions-considered-harmful/
-
-
-## What is being developed? (Roadmap)
-
-* First simple core achieved in simulation Sep 2020
- - FPGA (ECP5) target followed shortly
-* First silicon tape-out 180nm deadline 2nd Dec 2020
- - sponsored by NLnet, with help from Chips4Makers Libre Cell Libraries
- - layout is entirely libre-licensed tools: coriolis2 from lip6.fr
-* Next chip is "SBC" style quad-core
- - similar spec to Allwinner A64, Rockchip RK3399
- - targets "Pi" boards, smartphones, tablets, Industrial IoT
-
-## Contact
-
-* Freenode IRC #libre-soc
-* Website https://libre-soc.org
- - mailing list, git repos, bugtracker etc.
# FOSDEM 2021 OpenPOWER
-TODO https://penta.fosdem.org/submission/FOSDEM21/events
+* [[conferences/fosdem2021]]
+
+# LinuxConf 2021
+
+* <https://lca2021.linux.org.au/schedule/presentation/78/>
+
+# Europython 2021
+
+march for CfP
+
+* <https://ep2021.europython.eu/faq/#nodes>
+
+# 3mdeb beer event
+
+* <https://live.evenea.com/3mdeb-vbeer>
+
+# ICS2021
+
+* <https://ics21.github.io/>
+
+# FSIC2021
+
+* <https://wiki.f-si.org/index.php/FSiC2021#Tentative_program>
+
+# NGI Forum 2021
+
+* <https://2021.ngiforum.eu/>
+
+# 3mdeb beer event v2
+
+* <http://vpub.3mdeb.com/may7th>, 7th May at 3PM UTC
projects / libreriscv.git / blobdiff