MEM: Add port proxies instead of non-structural ports

[gem5.git] / configs / common / Caches.py

diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index f1ea957b5403e0e2c9e2848af599711914b5a45f..0be8001d782a9735e6e6b60b009e20cc6878bc10 100644 (file)
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -26,7 +26,6 @@
 #
 # Authors: Lisa Hsu
 
-import m5
 from m5.objects import *
 
 class L1Cache(BaseCache):
@@ -34,7 +33,8 @@ class L1Cache(BaseCache):
     block_size = 64
     latency = '1ns'
     mshrs = 10
-    tgts_per_mshr = 5
+    tgts_per_mshr = 20
+    is_top_level = True
 
 class L2Cache(BaseCache):
     assoc = 8
@@ -43,6 +43,15 @@ class L2Cache(BaseCache):
     mshrs = 20
     tgts_per_mshr = 12
 
+class PageTableWalkerCache(BaseCache):
+    assoc = 2
+    block_size = 64
+    latency = '1ns'
+    mshrs = 10
+    size = '1kB'
+    tgts_per_mshr = 12
+    is_top_level = True
+
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
@@ -50,3 +59,5 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
+    forward_snoops = False
+    is_top_level = True