configs: Remove Python 2.7 glue code

[gem5.git] / configs / common / Caches.py

diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 43a1c6378fac90b4ce5aa61a5c06ebd1b74b6397..1468b953c74358f84b1c9151e0bd63a117fa4da9 100644 (file)
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -1,3 +1,16 @@
+# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -23,23 +36,63 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Lisa Hsu
 
-import m5
+from m5.defines import buildEnv
 from m5.objects import *
 
-class L1Cache(BaseCache):
+# Base implementations of L1, L2, IO and TLB-walker caches. There are
+# used in the regressions and also as base components in the
+# system-configuration scripts. The values are meant to serve as a
+# starting point, and specific parameters can be overridden in the
+# specific instantiations.
+
+class L1Cache(Cache):
     assoc = 2
-    block_size = 64
-    latency = '1ns'
-    mshrs = 10
-    tgts_per_mshr = 5
+    tag_latency = 2
+    data_latency = 2
+    response_latency = 2
+    mshrs = 4
+    tgts_per_mshr = 20
+
+class L1_ICache(L1Cache):
+    is_read_only = True
+    # Writeback clean lines as well
+    writeback_clean = True
+
+class L1_DCache(L1Cache):
+    pass
 
-class L2Cache(BaseCache):
+class L2Cache(Cache):
     assoc = 8
-    block_size = 64
-    latency = '10ns'
+    tag_latency = 20
+    data_latency = 20
+    response_latency = 20
     mshrs = 20
     tgts_per_mshr = 12
+    write_buffers = 8
+
+class IOCache(Cache):
+    assoc = 8
+    tag_latency = 50
+    data_latency = 50
+    response_latency = 50
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+
+class PageTableWalkerCache(Cache):
+    assoc = 2
+    tag_latency = 2
+    data_latency = 2
+    response_latency = 2
+    mshrs = 10
+    size = '1kB'
+    tgts_per_mshr = 12
 
+    # the x86 table walker actually writes to the table-walker cache
+    if buildEnv['TARGET_ISA'] in ['x86', 'riscv']:
+        is_read_only = False
+    else:
+        is_read_only = True
+        # Writeback clean lines as well
+        writeback_clean = True