mem: More descriptive DRAM config names

[gem5.git] / configs / common / Caches.py

diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 0b5f9e1823ab5885438b761da244ca9ffe020bd1..6f1aff4430d273d68e4dc5340dbc514b97f84756 100644 (file)
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -40,12 +40,18 @@
 
 from m5.objects import *
 
+# Base implementations of L1, L2, IO and TLB-walker caches. There are
+# used in the regressions and also as base components in the
+# system-configuration scripts. The values are meant to serve as a
+# starting point, and specific parameters can be overridden in the
+# specific instantiations.
+
 class L1Cache(BaseCache):
     assoc = 2
-    block_size = 64
     hit_latency = 2
     response_latency = 2
-    mshrs = 10
+    block_size = 64
+    mshrs = 4
     tgts_per_mshr = 20
     is_top_level = True
 
@@ -56,16 +62,7 @@ class L2Cache(BaseCache):
     response_latency = 20
     mshrs = 20
     tgts_per_mshr = 12
-
-class PageTableWalkerCache(BaseCache):
-    assoc = 2
-    block_size = 64
-    hit_latency = 2
-    response_latency = 2
-    mshrs = 10
-    size = '1kB'
-    tgts_per_mshr = 12
-    is_top_level = True
+    write_buffers = 8
 
 class IOCache(BaseCache):
     assoc = 8
@@ -77,3 +74,13 @@ class IOCache(BaseCache):
     tgts_per_mshr = 12
     forward_snoops = False
     is_top_level = True
+
+class PageTableWalkerCache(BaseCache):
+    assoc = 2
+    block_size = 64
+    hit_latency = 2
+    response_latency = 2
+    mshrs = 10
+    size = '1kB'
+    tgts_per_mshr = 12
+    is_top_level = True