Merge zizzer.eecs.umich.edu:/bk/newmem

[gem5.git] / configs / common / FSConfig.py

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 5b0de2d6da774935d0f54fccb56bb9388eb3500f..289a7a5f4b391912b8eb8db1e42a0f836f41f203 100644 (file)
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -27,13 +27,9 @@
 # Authors: Kevin Lim
 
 import m5
+from m5 import makeList
 from m5.objects import *
-from FullO3Config import *
-from SysPaths import *
-from Util import *
-
-script.dir =  '/z/saidi/work/m5.newmem/configs/boot'
-linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img'))
+from Benchmarks import *
 
 class CowIdeDisk(IdeDisk):
     image = CowDiskImage(child=RawDiskImage(read_only=True),
@@ -42,6 +38,14 @@ class CowIdeDisk(IdeDisk):
     def childImage(self, ci):
         self.image.child.image_file = ci
 
+class CowMmDisk(MmDisk):
+    image = CowDiskImage(child=RawDiskImage(read_only=True),
+                         read_only=False)
+
+    def childImage(self, ci):
+        self.image.child.image_file = ci
+
+
 class BaseTsunami(Tsunami):
     ethernet = NSGigE(configdata=NSGigEPciData(),
                       pci_bus=0, pci_dev=1, pci_func=0)
@@ -49,38 +53,32 @@ class BaseTsunami(Tsunami):
     ide = IdeController(disks=[Parent.disk0, Parent.disk2],
                         pci_func=0, pci_dev=0, pci_bus=0)
 
-def MyLinuxAlphaSystem(cpu, mem_mode, linux_image, icache=None, dcache=None, l2cache=None):
+def makeLinuxAlphaSystem(mem_mode, mdesc = None):
     self = LinuxAlphaSystem()
+    if not mdesc:
+        # generic system
+        mdesc = SysConfig()
+    self.readfile = mdesc.script()
     self.iobus = Bus(bus_id=0)
     self.membus = Bus(bus_id=1)
-    self.bridge = Bridge()
-    self.physmem = PhysicalMemory(range = AddrRange('128MB'))
+    self.bridge = Bridge(fix_partial_write_b=True)
+    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
     self.bridge.side_a = self.iobus.port
     self.bridge.side_b = self.membus.port
     self.physmem.port = self.membus.port
     self.disk0 = CowIdeDisk(driveID='master')
     self.disk2 = CowIdeDisk(driveID='master')
-    self.disk0.childImage(linux_image)
+    self.disk0.childImage(mdesc.disk())
     self.disk2.childImage(disk('linux-bigswap2.img'))
     self.tsunami = BaseTsunami()
     self.tsunami.attachIO(self.iobus)
     self.tsunami.ide.pio = self.iobus.port
-    self.tsunami.ide.dma = self.iobus.port
-    self.tsunami.ide.config = self.iobus.port
     self.tsunami.ethernet.pio = self.iobus.port
-    self.tsunami.ethernet.dma = self.iobus.port
-    self.tsunami.ethernet.config = self.iobus.port
-    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image,
+    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
                                                read_only = True))
     self.intrctrl = IntrControl()
-    self.cpu = cpu
-
-    connectCpu(self.cpu, self.membus, icache, dcache, l2cache)
-    for each_cpu in listWrapper(self.cpu):
-        each_cpu.itb = AlphaITB()
-        each_cpu.dtb = AlphaDTB()
-    self.cpu.clock = '2GHz'
-    self.sim_console = SimConsole(listener=ConsoleListener(port=3456))
+    self.mem_mode = mem_mode
+    self.sim_console = SimConsole()
     self.kernel = binary('vmlinux')
     self.pal = binary('ts_osfpal')
     self.console = binary('console')
@@ -88,17 +86,50 @@ def MyLinuxAlphaSystem(cpu, mem_mode, linux_image, icache=None, dcache=None, l2c
 
     return self
 
-class TsunamiRoot(Root):
-    pass
+def makeSparcSystem(mem_mode, mdesc = None):
+    self = SparcSystem()
+    if not mdesc:
+        # generic system
+        mdesc = SysConfig()
+    self.readfile = mdesc.script()
+    self.iobus = Bus(bus_id=0)
+    self.membus = Bus(bus_id=1)
+    self.bridge = Bridge()
+    self.t1000 = T1000()
+    self.t1000.attachOnChipIO(self.membus)
+    self.t1000.attachIO(self.iobus)
+    self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
+    self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
+    self.bridge.side_a = self.iobus.port
+    self.bridge.side_b = self.membus.port
+    self.physmem.port = self.membus.port
+    self.physmem2.port = self.membus.port
+    self.rom.port = self.membus.port
+    self.nvram.port = self.membus.port
+    self.hypervisor_desc.port = self.membus.port
+    self.partition_desc.port = self.membus.port
+    self.intrctrl = IntrControl()
+    self.disk0 = CowMmDisk()
+    self.disk0.childImage(disk('disk.s10hw2'))
+    self.disk0.pio = self.iobus.port
+    self.reset_bin = binary('reset_new.bin')
+    self.hypervisor_bin = binary('q_new.bin')
+    self.openboot_bin = binary('openboot_new.bin')
+    self.nvram_bin = binary('nvram1')
+    self.hypervisor_desc_bin = binary('1up-hv.bin')
+    self.partition_desc_bin = binary('1up-md.bin')
+
+    return self
+
 
-def DualRoot(clientSystem, serverSystem):
+def makeDualRoot(testSystem, driveSystem, dumpfile):
     self = Root()
-    self.client = clientSystem
-    self.server = serverSystem
+    self.testsys = testSystem
+    self.drivesys = driveSystem
+    self.etherlink = EtherLink(int1 = Parent.testsys.tsunami.etherint[0],
+                               int2 = Parent.drivesys.tsunami.etherint[0])
+    if dumpfile:
+        self.etherdump = EtherDump(file=dumpfile)
+        self.etherlink.dump = Parent.etherdump
 
-    self.etherdump = EtherDump(file='ethertrace')
-    self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0],
-                               int2 = Parent.server.tsunami.etherint[0],
-                               dump = Parent.etherdump)
-    self.clock = '1THz'
     return self