Merge zizzer.eecs.umich.edu:/bk/newmem

[gem5.git] / configs / common / FSConfig.py

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 67a1e57356392a519cf68b9a839e537287891792..289a7a5f4b391912b8eb8db1e42a0f836f41f203 100644 (file)
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -30,7 +30,6 @@ import m5
 from m5 import makeList
 from m5.objects import *
 from Benchmarks import *
-from FullO3Config import *
 
 class CowIdeDisk(IdeDisk):
     image = CowDiskImage(child=RawDiskImage(read_only=True),
@@ -39,6 +38,14 @@ class CowIdeDisk(IdeDisk):
     def childImage(self, ci):
         self.image.child.image_file = ci
 
+class CowMmDisk(MmDisk):
+    image = CowDiskImage(child=RawDiskImage(read_only=True),
+                         read_only=False)
+
+    def childImage(self, ci):
+        self.image.child.image_file = ci
+
+
 class BaseTsunami(Tsunami):
     ethernet = NSGigE(configdata=NSGigEPciData(),
                       pci_bus=0, pci_dev=1, pci_func=0)
@@ -50,11 +57,11 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
     self = LinuxAlphaSystem()
     if not mdesc:
         # generic system
-        mdesc = Machine()
+        mdesc = SysConfig()
     self.readfile = mdesc.script()
     self.iobus = Bus(bus_id=0)
     self.membus = Bus(bus_id=1)
-    self.bridge = Bridge()
+    self.bridge = Bridge(fix_partial_write_b=True)
     self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
     self.bridge.side_a = self.iobus.port
     self.bridge.side_b = self.membus.port
@@ -71,7 +78,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
                                                read_only = True))
     self.intrctrl = IntrControl()
     self.mem_mode = mem_mode
-    self.sim_console = SimConsole(listener=ConsoleListener(port=3456))
+    self.sim_console = SimConsole()
     self.kernel = binary('vmlinux')
     self.pal = binary('ts_osfpal')
     self.console = binary('console')
@@ -79,6 +86,42 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
 
     return self
 
+def makeSparcSystem(mem_mode, mdesc = None):
+    self = SparcSystem()
+    if not mdesc:
+        # generic system
+        mdesc = SysConfig()
+    self.readfile = mdesc.script()
+    self.iobus = Bus(bus_id=0)
+    self.membus = Bus(bus_id=1)
+    self.bridge = Bridge()
+    self.t1000 = T1000()
+    self.t1000.attachOnChipIO(self.membus)
+    self.t1000.attachIO(self.iobus)
+    self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
+    self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
+    self.bridge.side_a = self.iobus.port
+    self.bridge.side_b = self.membus.port
+    self.physmem.port = self.membus.port
+    self.physmem2.port = self.membus.port
+    self.rom.port = self.membus.port
+    self.nvram.port = self.membus.port
+    self.hypervisor_desc.port = self.membus.port
+    self.partition_desc.port = self.membus.port
+    self.intrctrl = IntrControl()
+    self.disk0 = CowMmDisk()
+    self.disk0.childImage(disk('disk.s10hw2'))
+    self.disk0.pio = self.iobus.port
+    self.reset_bin = binary('reset_new.bin')
+    self.hypervisor_bin = binary('q_new.bin')
+    self.openboot_bin = binary('openboot_new.bin')
+    self.nvram_bin = binary('nvram1')
+    self.hypervisor_desc_bin = binary('1up-hv.bin')
+    self.partition_desc_bin = binary('1up-md.bin')
+
+    return self
+
+
 def makeDualRoot(testSystem, driveSystem, dumpfile):
     self = Root()
     self.testsys = testSystem
@@ -89,5 +132,4 @@ def makeDualRoot(testSystem, driveSystem, dumpfile):
         self.etherdump = EtherDump(file=dumpfile)
         self.etherlink.dump = Parent.etherdump
 
-    self.clock = '1THz'
     return self