+# Copyright (c) 2010 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
# Copyright (c) 2006-2008 The Regents of The University of Michigan
# All rights reserved.
#
from m5.objects import *
from Benchmarks import *
+from m5.util import convert
class CowIdeDisk(IdeDisk):
image = CowDiskImage(child=RawDiskImage(read_only=True),
self.tsunami.ethernet.pio = self.piobus.port
#
- # store the dma devices for later connection to dma ruby ports
+ # Store the dma devices for later connection to dma ruby ports.
+ # Append an underscore to dma_devices to avoid the SimObjectVector check.
#
- self.dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
+ self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
return self
+def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
+ assert machine_type
+
+ if bare_metal:
+ self = ArmSystem()
+ else:
+ self = LinuxArmSystem()
+
+ if not mdesc:
+ # generic system
+ mdesc = SysConfig()
+
+ self.readfile = mdesc.script()
+ self.iobus = Bus(bus_id=0)
+ self.membus = MemBus(bus_id=1)
+ self.membus.badaddr_responder.warn_access = "warn"
+ self.bridge = Bridge(delay='50ns', nack_delay='4ns')
+ self.bridge.side_a = self.iobus.port
+ self.bridge.side_b = self.membus.port
+
+ self.mem_mode = mem_mode
+
+ if machine_type == "RealView_PBX":
+ self.realview = RealViewPBX()
+ elif machine_type == "RealView_EB":
+ self.realview = RealViewEB()
+ elif machine_type == "VExpress_ELT":
+ self.realview = VExpress_ELT()
+ else:
+ print "Unknown Machine Type"
+ sys.exit(1)
+
+ self.cf0 = CowIdeDisk(driveID='master')
+ self.cf0.childImage(mdesc.disk())
+ # default to an IDE controller rather than a CF one
+ # assuming we've got one
+ try:
+ self.realview.ide.disks = [self.cf0]
+ except:
+ self.realview.cf_ctrl.disks = [self.cf0]
+
+ if bare_metal:
+ # EOT character on UART will end the simulation
+ self.realview.uart.end_on_eot = True
+ self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())),
+ zero = True)
+ else:
+ self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
+ self.machine_type = machine_type
+ if convert.toMemorySize(mdesc.mem()) > convert.toMemorySize('256MB'):
+ print "The currently implemented ARM platforms only easily support 256MB of DRAM"
+ print "It might be possible to get some more by using 256MB@0x30000000, but this"
+ print "is untested and may require some heroics"
+
+ boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
+ 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
+
+ self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())),
+ zero = True)
+ self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'),
+ size = '64MB'), zero = True)
+ self.nvmem.port = self.membus.port
+ self.boot_loader = binary('boot.arm')
+ self.boot_loader_mem = self.nvmem
+ self.gic_cpu_addr = self.realview.gic.cpu_addr
+ self.flags_addr = self.realview.realview_io.pio_addr + 0x30
+
+ if mdesc.disk().lower().count('android'):
+ boot_flags += " init=/init "
+ self.boot_osflags = boot_flags
+
+ self.physmem.port = self.membus.port
+ self.realview.attachOnChipIO(self.membus)
+ self.realview.attachIO(self.iobus)
+ self.intrctrl = IntrControl()
+ self.terminal = Terminal()
+ self.vncserver = VncServer()
+
+ return self
+
+
def makeLinuxMipsSystem(mem_mode, mdesc = None):
class BaseMalta(Malta):
ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
def x86IOAddress(port):
IO_address_space_base = 0x8000000000000000
- return IO_address_space_base + port;
+ return IO_address_space_base + port
-def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None):
+def connectX86ClassicSystem(x86_sys):
+ x86_sys.membus = MemBus(bus_id=1)
+ x86_sys.physmem.port = x86_sys.membus.port
+
+ # North Bridge
+ x86_sys.iobus = Bus(bus_id=0)
+ x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
+ x86_sys.bridge.side_a = x86_sys.iobus.port
+ x86_sys.bridge.side_b = x86_sys.membus.port
+
+ # connect the io bus
+ x86_sys.pc.attachIO(x86_sys.iobus)
+
+def connectX86RubySystem(x86_sys):
+ # North Bridge
+ x86_sys.piobus = Bus(bus_id=0)
+
+ #
+ # Pio functional accesses from devices need direct access to memory
+ # RubyPort currently does support functional accesses. Therefore provide
+ # the piobus a direct connection to physical memory
+ #
+ x86_sys.piobus.port = x86_sys.physmem.port
+
+ x86_sys.pc.attachIO(x86_sys.piobus)
+
+
+def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
if self == None:
self = X86System()
if not mdesc:
# generic system
mdesc = SysConfig()
- mdesc.diskname = 'x86root.img'
self.readfile = mdesc.script()
self.mem_mode = mem_mode
# Physical memory
- self.membus = MemBus(bus_id=1)
self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
- self.physmem.port = self.membus.port
-
- # North Bridge
- self.iobus = Bus(bus_id=0)
- self.bridge = Bridge(delay='50ns', nack_delay='4ns')
- self.bridge.side_a = self.iobus.port
- self.bridge.side_b = self.membus.port
# Platform
self.pc = Pc()
- self.pc.attachIO(self.iobus)
+
+ # Create and connect the busses required by each memory system
+ if Ruby:
+ connectX86RubySystem(self)
+ # add the ide to the list of dma devices that later need to attach to
+ # dma controllers
+ self._dma_devices = [self.pc.south_bridge.ide]
+ else:
+ connectX86ClassicSystem(self)
self.intrctrl = IntrControl()
self.smbios_table.structures = structures
# Set up the Intel MP table
+ base_entries = []
+ ext_entries = []
for i in xrange(numCPUs):
bp = X86IntelMPProcessor(
local_apic_id = i,
local_apic_version = 0x14,
enable = True,
bootstrap = (i == 0))
- self.intel_mp_table.add_entry(bp)
+ base_entries.append(bp)
io_apic = X86IntelMPIOAPIC(
id = numCPUs,
version = 0x11,
enable = True,
address = 0xfec00000)
self.pc.south_bridge.io_apic.apic_id = io_apic.id
- self.intel_mp_table.add_entry(io_apic)
+ base_entries.append(io_apic)
isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
- self.intel_mp_table.add_entry(isa_bus)
+ base_entries.append(isa_bus)
pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
- self.intel_mp_table.add_entry(pci_bus)
+ base_entries.append(pci_bus)
connect_busses = X86IntelMPBusHierarchy(bus_id=0,
subtractive_decode=True, parent_bus=1)
- self.intel_mp_table.add_entry(connect_busses)
+ ext_entries.append(connect_busses)
pci_dev4_inta = X86IntelMPIOIntAssignment(
interrupt_type = 'INT',
polarity = 'ConformPolarity',
source_bus_irq = 0 + (4 << 2),
dest_io_apic_id = io_apic.id,
dest_io_apic_intin = 16)
- self.intel_mp_table.add_entry(pci_dev4_inta);
+ base_entries.append(pci_dev4_inta)
def assignISAInt(irq, apicPin):
assign_8259_to_apic = X86IntelMPIOIntAssignment(
interrupt_type = 'ExtInt',
source_bus_irq = irq,
dest_io_apic_id = io_apic.id,
dest_io_apic_intin = 0)
- self.intel_mp_table.add_entry(assign_8259_to_apic)
+ base_entries.append(assign_8259_to_apic)
assign_to_apic = X86IntelMPIOIntAssignment(
interrupt_type = 'INT',
polarity = 'ConformPolarity',
source_bus_irq = irq,
dest_io_apic_id = io_apic.id,
dest_io_apic_intin = apicPin)
- self.intel_mp_table.add_entry(assign_to_apic)
+ base_entries.append(assign_to_apic)
assignISAInt(0, 2)
assignISAInt(1, 1)
for i in range(3, 15):
assignISAInt(i, i)
-
-
-def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None):
+ self.intel_mp_table.base_entries = base_entries
+ self.intel_mp_table.ext_entries = ext_entries
+
+def setWorkCountOptions(system, options):
+ if options.work_item_id != None:
+ system.work_item_id = options.work_item_id
+ if options.work_begin_cpu_id_exit != None:
+ system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit
+ if options.work_end_exit_count != None:
+ system.work_end_exit_count = options.work_end_exit_count
+ if options.work_end_checkpoint_count != None:
+ system.work_end_ckpt_count = options.work_end_checkpoint_count
+ if options.work_begin_exit_count != None:
+ system.work_begin_exit_count = options.work_begin_exit_count
+ if options.work_begin_checkpoint_count != None:
+ system.work_begin_ckpt_count = options.work_begin_checkpoint_count
+ if options.work_cpus_checkpoint_count != None:
+ system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count
+
+
+def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
self = LinuxX86System()
- # Build up a generic x86 system and then specialize it for Linux
- makeX86System(mem_mode, numCPUs, mdesc, self)
+ # Build up the x86 system and then specialize it for Linux
+ makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
# We assume below that there's at least 1MB of memory. We'll require 2
# just to avoid corner cases.
assert(self.physmem.range.second.getValue() >= 0x200000)
- # Mark the first megabyte of memory as reserved
- self.e820_table.entries.append(X86E820Entry(
- addr = 0,
- size = '1MB',
- range_type = 2))
-
- # Mark the rest as available
- self.e820_table.entries.append(X86E820Entry(
- addr = 0x100000,
+ self.e820_table.entries = \
+ [
+ # Mark the first megabyte of memory as reserved
+ X86E820Entry(addr = 0, size = '1MB', range_type = 2),
+ # Mark the rest as available
+ X86E820Entry(addr = 0x100000,
size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
- range_type = 1))
+ range_type = 1)
+ ]
# Command line
self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
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