-# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2010 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
+# Copyright (c) 2006-2008 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
#
# Authors: Kevin Lim
-import m5
-from m5 import makeList
from m5.objects import *
from Benchmarks import *
+from m5.util import convert
class CowIdeDisk(IdeDisk):
image = CowDiskImage(child=RawDiskImage(read_only=True),
def childImage(self, ci):
self.image.child.image_file = ci
+class MemBus(Bus):
+ badaddr_responder = BadAddr()
+ default = Self.badaddr_responder.pio
+
+
def makeLinuxAlphaSystem(mem_mode, mdesc = None):
class BaseTsunami(Tsunami):
- ethernet = NSGigE(configdata=NSGigEPciData(),
- pci_bus=0, pci_dev=1, pci_func=0)
- etherint = NSGigEInt(device=Parent.ethernet)
+ ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
pci_func=0, pci_dev=0, pci_bus=0)
mdesc = SysConfig()
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
- self.membus = Bus(bus_id=1)
+ self.membus = MemBus(bus_id=1)
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
self.bridge.side_a = self.iobus.port
read_only = True))
self.intrctrl = IntrControl()
self.mem_mode = mem_mode
- self.sim_console = SimConsole()
+ self.terminal = Terminal()
+ self.kernel = binary('vmlinux')
+ self.pal = binary('ts_osfpal')
+ self.console = binary('console')
+ self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
+
+ return self
+
+def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
+ class BaseTsunami(Tsunami):
+ ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
+ ide = IdeController(disks=[Parent.disk0, Parent.disk2],
+ pci_func=0, pci_dev=0, pci_bus=0)
+
+ physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
+ self = LinuxAlphaSystem(physmem = physmem)
+ if not mdesc:
+ # generic system
+ mdesc = SysConfig()
+ self.readfile = mdesc.script()
+
+ # Create pio bus to connect all device pio ports to rubymem's pio port
+ self.piobus = Bus(bus_id=0)
+
+ #
+ # Pio functional accesses from devices need direct access to memory
+ # RubyPort currently does support functional accesses. Therefore provide
+ # the piobus a direct connection to physical memory
+ #
+ self.piobus.port = physmem.port
+
+ self.disk0 = CowIdeDisk(driveID='master')
+ self.disk2 = CowIdeDisk(driveID='master')
+ self.disk0.childImage(mdesc.disk())
+ self.disk2.childImage(disk('linux-bigswap2.img'))
+ self.tsunami = BaseTsunami()
+ self.tsunami.attachIO(self.piobus)
+ self.tsunami.ide.pio = self.piobus.port
+ self.tsunami.ethernet.pio = self.piobus.port
+
+ #
+ # Store the dma devices for later connection to dma ruby ports.
+ # Append an underscore to dma_devices to avoid the SimObjectVector check.
+ #
+ self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
+
+ self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
+ read_only = True))
+ self.intrctrl = IntrControl()
+ self.mem_mode = mem_mode
+ self.terminal = Terminal()
self.kernel = binary('vmlinux')
self.pal = binary('ts_osfpal')
self.console = binary('console')
mdesc = SysConfig()
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
- self.membus = Bus(bus_id=1)
- self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns')
+ self.membus = MemBus(bus_id=1)
+ self.bridge = Bridge(delay='50ns', nack_delay='4ns')
self.t1000 = T1000()
self.t1000.attachOnChipIO(self.membus)
self.t1000.attachIO(self.iobus)
return self
+def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
+ assert machine_type
+
+ if bare_metal:
+ self = ArmSystem()
+ else:
+ self = LinuxArmSystem()
+
+ if not mdesc:
+ # generic system
+ mdesc = SysConfig()
+
+ self.readfile = mdesc.script()
+ self.iobus = Bus(bus_id=0)
+ self.membus = MemBus(bus_id=1)
+ self.membus.badaddr_responder.warn_access = "warn"
+ self.bridge = Bridge(delay='50ns', nack_delay='4ns')
+ self.bridge.side_a = self.iobus.port
+ self.bridge.side_b = self.membus.port
+
+ self.mem_mode = mem_mode
+
+ if machine_type == "RealView_PBX":
+ self.realview = RealViewPBX()
+ elif machine_type == "RealView_EB":
+ self.realview = RealViewEB()
+ elif machine_type == "VExpress_ELT":
+ self.realview = VExpress_ELT()
+ else:
+ print "Unknown Machine Type"
+ sys.exit(1)
+
+ self.cf0 = CowIdeDisk(driveID='master')
+ self.cf0.childImage(mdesc.disk())
+ # default to an IDE controller rather than a CF one
+ # assuming we've got one
+ try:
+ self.realview.ide.disks = [self.cf0]
+ except:
+ self.realview.cf_ctrl.disks = [self.cf0]
+
+ if bare_metal:
+ # EOT character on UART will end the simulation
+ self.realview.uart.end_on_eot = True
+ self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())),
+ zero = True)
+ else:
+ self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
+ self.machine_type = machine_type
+ if convert.toMemorySize(mdesc.mem()) > convert.toMemorySize('256MB'):
+ print "The currently implemented ARM platforms only easily support 256MB of DRAM"
+ print "It might be possible to get some more by using 256MB@0x30000000, but this"
+ print "is untested and may require some heroics"
+
+ boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
+ 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
+
+ self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())),
+ zero = True)
+ self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'),
+ size = '64MB'), zero = True)
+ self.nvmem.port = self.membus.port
+ self.boot_loader = binary('boot.arm')
+ self.boot_loader_mem = self.nvmem
+ self.gic_cpu_addr = self.realview.gic.cpu_addr
+ self.flags_addr = self.realview.realview_io.pio_addr + 0x30
+
+ if mdesc.disk().lower().count('android'):
+ boot_flags += " init=/init "
+ self.boot_osflags = boot_flags
+
+ self.physmem.port = self.membus.port
+ self.realview.attachOnChipIO(self.membus)
+ self.realview.attachIO(self.iobus)
+ self.intrctrl = IntrControl()
+ self.terminal = Terminal()
+ self.vncserver = VncServer()
+
+ return self
+
+
+def makeLinuxMipsSystem(mem_mode, mdesc = None):
+ class BaseMalta(Malta):
+ ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
+ ide = IdeController(disks=[Parent.disk0, Parent.disk2],
+ pci_func=0, pci_dev=0, pci_bus=0)
+
+ self = LinuxMipsSystem()
+ if not mdesc:
+ # generic system
+ mdesc = SysConfig()
+ self.readfile = mdesc.script()
+ self.iobus = Bus(bus_id=0)
+ self.membus = MemBus(bus_id=1)
+ self.bridge = Bridge(delay='50ns', nack_delay='4ns')
+ self.physmem = PhysicalMemory(range = AddrRange('1GB'))
+ self.bridge.side_a = self.iobus.port
+ self.bridge.side_b = self.membus.port
+ self.physmem.port = self.membus.port
+ self.disk0 = CowIdeDisk(driveID='master')
+ self.disk2 = CowIdeDisk(driveID='master')
+ self.disk0.childImage(mdesc.disk())
+ self.disk2.childImage(disk('linux-bigswap2.img'))
+ self.malta = BaseMalta()
+ self.malta.attachIO(self.iobus)
+ self.malta.ide.pio = self.iobus.port
+ self.malta.ethernet.pio = self.iobus.port
+ self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
+ read_only = True))
+ self.intrctrl = IntrControl()
+ self.mem_mode = mem_mode
+ self.terminal = Terminal()
+ self.kernel = binary('mips/vmlinux')
+ self.console = binary('mips/console')
+ self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
+
+ return self
+
+def x86IOAddress(port):
+ IO_address_space_base = 0x8000000000000000
+ return IO_address_space_base + port
+
+def connectX86ClassicSystem(x86_sys):
+ x86_sys.membus = MemBus(bus_id=1)
+ x86_sys.physmem.port = x86_sys.membus.port
+
+ # North Bridge
+ x86_sys.iobus = Bus(bus_id=0)
+ x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
+ x86_sys.bridge.side_a = x86_sys.iobus.port
+ x86_sys.bridge.side_b = x86_sys.membus.port
+
+ # connect the io bus
+ x86_sys.pc.attachIO(x86_sys.iobus)
+
+def connectX86RubySystem(x86_sys):
+ # North Bridge
+ x86_sys.piobus = Bus(bus_id=0)
+
+ #
+ # Pio functional accesses from devices need direct access to memory
+ # RubyPort currently does support functional accesses. Therefore provide
+ # the piobus a direct connection to physical memory
+ #
+ x86_sys.piobus.port = x86_sys.physmem.port
+
+ x86_sys.pc.attachIO(x86_sys.piobus)
+
+
+def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
+ if self == None:
+ self = X86System()
+
+ if not mdesc:
+ # generic system
+ mdesc = SysConfig()
+ self.readfile = mdesc.script()
+
+ self.mem_mode = mem_mode
+
+ # Physical memory
+ self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
+
+ # Platform
+ self.pc = Pc()
+
+ # Create and connect the busses required by each memory system
+ if Ruby:
+ connectX86RubySystem(self)
+ # add the ide to the list of dma devices that later need to attach to
+ # dma controllers
+ self._dma_devices = [self.pc.south_bridge.ide]
+ else:
+ connectX86ClassicSystem(self)
+
+ self.intrctrl = IntrControl()
+
+ # Disks
+ disk0 = CowIdeDisk(driveID='master')
+ disk2 = CowIdeDisk(driveID='master')
+ disk0.childImage(mdesc.disk())
+ disk2.childImage(disk('linux-bigswap2.img'))
+ self.pc.south_bridge.ide.disks = [disk0, disk2]
+
+ # Add in a Bios information structure.
+ structures = [X86SMBiosBiosInformation()]
+ self.smbios_table.structures = structures
+
+ # Set up the Intel MP table
+ base_entries = []
+ ext_entries = []
+ for i in xrange(numCPUs):
+ bp = X86IntelMPProcessor(
+ local_apic_id = i,
+ local_apic_version = 0x14,
+ enable = True,
+ bootstrap = (i == 0))
+ base_entries.append(bp)
+ io_apic = X86IntelMPIOAPIC(
+ id = numCPUs,
+ version = 0x11,
+ enable = True,
+ address = 0xfec00000)
+ self.pc.south_bridge.io_apic.apic_id = io_apic.id
+ base_entries.append(io_apic)
+ isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
+ base_entries.append(isa_bus)
+ pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
+ base_entries.append(pci_bus)
+ connect_busses = X86IntelMPBusHierarchy(bus_id=0,
+ subtractive_decode=True, parent_bus=1)
+ ext_entries.append(connect_busses)
+ pci_dev4_inta = X86IntelMPIOIntAssignment(
+ interrupt_type = 'INT',
+ polarity = 'ConformPolarity',
+ trigger = 'ConformTrigger',
+ source_bus_id = 1,
+ source_bus_irq = 0 + (4 << 2),
+ dest_io_apic_id = io_apic.id,
+ dest_io_apic_intin = 16)
+ base_entries.append(pci_dev4_inta)
+ def assignISAInt(irq, apicPin):
+ assign_8259_to_apic = X86IntelMPIOIntAssignment(
+ interrupt_type = 'ExtInt',
+ polarity = 'ConformPolarity',
+ trigger = 'ConformTrigger',
+ source_bus_id = 0,
+ source_bus_irq = irq,
+ dest_io_apic_id = io_apic.id,
+ dest_io_apic_intin = 0)
+ base_entries.append(assign_8259_to_apic)
+ assign_to_apic = X86IntelMPIOIntAssignment(
+ interrupt_type = 'INT',
+ polarity = 'ConformPolarity',
+ trigger = 'ConformTrigger',
+ source_bus_id = 0,
+ source_bus_irq = irq,
+ dest_io_apic_id = io_apic.id,
+ dest_io_apic_intin = apicPin)
+ base_entries.append(assign_to_apic)
+ assignISAInt(0, 2)
+ assignISAInt(1, 1)
+ for i in range(3, 15):
+ assignISAInt(i, i)
+ self.intel_mp_table.base_entries = base_entries
+ self.intel_mp_table.ext_entries = ext_entries
+
+def setWorkCountOptions(system, options):
+ if options.work_item_id != None:
+ system.work_item_id = options.work_item_id
+ if options.work_begin_cpu_id_exit != None:
+ system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit
+ if options.work_end_exit_count != None:
+ system.work_end_exit_count = options.work_end_exit_count
+ if options.work_end_checkpoint_count != None:
+ system.work_end_ckpt_count = options.work_end_checkpoint_count
+ if options.work_begin_exit_count != None:
+ system.work_begin_exit_count = options.work_begin_exit_count
+ if options.work_begin_checkpoint_count != None:
+ system.work_begin_ckpt_count = options.work_begin_checkpoint_count
+ if options.work_cpus_checkpoint_count != None:
+ system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count
+
+
+def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
+ self = LinuxX86System()
+
+ # Build up the x86 system and then specialize it for Linux
+ makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
+
+ # We assume below that there's at least 1MB of memory. We'll require 2
+ # just to avoid corner cases.
+ assert(self.physmem.range.second.getValue() >= 0x200000)
+
+ self.e820_table.entries = \
+ [
+ # Mark the first megabyte of memory as reserved
+ X86E820Entry(addr = 0, size = '1MB', range_type = 2),
+ # Mark the rest as available
+ X86E820Entry(addr = 0x100000,
+ size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
+ range_type = 1)
+ ]
+
+ # Command line
+ self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
+ 'root=/dev/hda1'
+ return self
+
def makeDualRoot(testSystem, driveSystem, dumpfile):
self = Root()
self.testsys = testSystem
self.drivesys = driveSystem
- self.etherlink = EtherLink(int1 = Parent.testsys.tsunami.etherint[0],
- int2 = Parent.drivesys.tsunami.etherint[0])
+ self.etherlink = EtherLink()
+ self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
+ self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
+
if dumpfile:
self.etherdump = EtherDump(file=dumpfile)
self.etherlink.dump = Parent.etherdump
return self
+
+def setMipsOptions(TestCPUClass):
+ #CP0 Configuration
+ TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
+ TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
+ TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
+ TestCPUClass.CoreParams.CP0_PRId_Revision = 0
+
+ #CP0 Interrupt Control
+ TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
+ TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
+
+ # Config Register
+ #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
+ #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
+ TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
+ TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
+ TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
+ TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
+ #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
+
+ #Config 1 Register
+ TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
+ TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
+ # ***VERY IMPORTANT***
+ # Remember to modify CP0_Config1 according to cache specs
+ # Examine file ../common/Cache.py
+ TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
+ TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
+ TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
+ TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
+ TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
+ TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
+ TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
+ TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
+ TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
+ TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
+ TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
+ TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
+ TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
+
+ #Config 2 Register
+ TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
+ TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
+ TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
+ TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
+ TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
+ TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
+ TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
+ TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
+ TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
+
+
+ #Config 3 Register
+ TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
+ TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
+ TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
+ TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
+ TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
+ TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
+ TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
+ TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
+ TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
+
+ #SRS Ctl - HSS
+ TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
+
+
+ #TestCPUClass.CoreParams.tlb = TLB()
+ #TestCPUClass.CoreParams.UnifiedTLB = 1
projects / gem5.git / blobdiff