-# Copyright (c) 2010-2012 ARM Limited
+# Copyright (c) 2010-2012, 2015-2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
#
# Authors: Kevin Lim
+from __future__ import print_function
+from __future__ import absolute_import
+
from m5.objects import *
-from Benchmarks import *
from m5.util import *
+from .Benchmarks import *
+from . import ObjectList
+
+# Populate to reflect supported os types per target ISA
+os_types = { 'alpha' : [ 'linux' ],
+ 'mips' : [ 'linux' ],
+ 'sparc' : [ 'linux' ],
+ 'x86' : [ 'linux' ],
+ 'arm' : [ 'linux',
+ 'android-gingerbread',
+ 'android-ics',
+ 'android-jellybean',
+ 'android-kitkat',
+ 'android-nougat', ],
+ }
class CowIdeDisk(IdeDisk):
image = CowDiskImage(child=RawDiskImage(read_only=True),
def childImage(self, ci):
self.image.child.image_file = ci
-class MemBus(CoherentXBar):
+class MemBus(SystemXBar):
badaddr_responder = BadAddr()
default = Self.badaddr_responder.pio
+def fillInCmdline(mdesc, template, **kwargs):
+ kwargs.setdefault('disk', mdesc.disk())
+ kwargs.setdefault('rootdev', mdesc.rootdev())
+ kwargs.setdefault('mem', mdesc.mem())
+ kwargs.setdefault('script', mdesc.script())
+ return template % kwargs
-def makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False):
+def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None):
class BaseTsunami(Tsunami):
ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
self.tsunami = BaseTsunami()
# Create the io bus to connect all device ports
- self.iobus = NoncoherentXBar()
+ self.iobus = IOXBar()
self.tsunami.attachIO(self.iobus)
self.tsunami.ide.pio = self.iobus.master
- self.tsunami.ide.config = self.iobus.master
self.tsunami.ethernet.pio = self.iobus.master
- self.tsunami.ethernet.config = self.iobus.master
if ruby:
# Store the dma devices for later connection to dma ruby ports.
self.intrctrl = IntrControl()
self.mem_mode = mem_mode
self.terminal = Terminal()
- self.kernel = binary('vmlinux')
self.pal = binary('ts_osfpal')
self.console = binary('console')
- self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
+ if not cmdline:
+ cmdline = 'root=/dev/hda1 console=ttyS0'
+ self.boot_osflags = fillInCmdline(mdesc, cmdline)
return self
-def makeSparcSystem(mem_mode, mdesc = None):
+def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
# Constants from iob.cc and uart8250.cc
iob_man_addr = 0x9800000000
uart_pio_size = 8
# generic system
mdesc = SysConfig()
self.readfile = mdesc.script()
- self.iobus = NoncoherentXBar()
+ self.iobus = IOXBar()
self.membus = MemBus()
self.bridge = Bridge(delay='50ns')
self.t1000 = T1000()
self.partition_desc.port = self.membus.master
self.intrctrl = IntrControl()
self.disk0 = CowMmDisk()
- self.disk0.childImage(disk('disk.s10hw2'))
+ self.disk0.childImage(mdesc.disk())
self.disk0.pio = self.iobus.master
# The puart0 and hvuart are placed on the IO bus, so create ranges
return self
-def makeArmSystem(mem_mode, machine_type, num_cpus = 1, mdesc = None,
- dtb_filename = None, bare_metal=False):
+def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
+ dtb_filename=None, bare_metal=False, cmdline=None,
+ external_memory="", ruby=False, security=False):
assert machine_type
+ pci_devices = []
+
if bare_metal:
self = ArmSystem()
else:
mdesc = SysConfig()
self.readfile = mdesc.script()
- self.iobus = NoncoherentXBar()
- self.membus = MemBus()
- self.membus.badaddr_responder.warn_access = "warn"
- self.bridge = Bridge(delay='50ns')
- self.bridge.master = self.iobus.slave
- self.bridge.slave = self.membus.master
+ self.iobus = IOXBar()
+ if not ruby:
+ self.bridge = Bridge(delay='50ns')
+ self.bridge.master = self.iobus.slave
+ self.membus = MemBus()
+ self.membus.badaddr_responder.warn_access = "warn"
+ self.bridge.slave = self.membus.master
self.mem_mode = mem_mode
- if machine_type == "RealView_PBX":
- self.realview = RealViewPBX()
- elif machine_type == "RealView_EB":
- self.realview = RealViewEB()
- elif machine_type == "VExpress_EMM":
- self.realview = VExpress_EMM()
- if not dtb_filename:
- dtb_filename = 'vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb' % num_cpus
- elif machine_type == "VExpress_EMM64":
- self.realview = VExpress_EMM64()
+ platform_class = ObjectList.platform_list.get(machine_type)
+ # Resolve the real platform name, the original machine_type
+ # variable might have been an alias.
+ machine_type = platform_class.__name__
+ self.realview = platform_class()
+ self._bootmem = self.realview.bootmem
+
+ if isinstance(self.realview, VExpress_EMM64):
if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img':
- print "Selected 64-bit ARM architecture, updating default disk image..."
+ print("Selected 64-bit ARM architecture, updating default "
+ "disk image...")
mdesc.diskname = 'linaro-minimal-aarch64.img'
- if not dtb_filename:
- dtb_filename = 'vexpress.aarch64.20140821.dtb'
- else:
- print "Unknown Machine Type"
- sys.exit(1)
- self.cf0 = CowIdeDisk(driveID='master')
- self.cf0.childImage(mdesc.disk())
# Attach any PCI devices this platform supports
self.realview.attachPciDevices()
- # default to an IDE controller rather than a CF one
- try:
+
+ self.cf0 = CowIdeDisk(driveID='master')
+ self.cf0.childImage(mdesc.disk())
+ # Old platforms have a built-in IDE or CF controller. Default to
+ # the IDE controller if both exist. New platforms expect the
+ # storage controller to be added from the config script.
+ if hasattr(self.realview, "ide"):
self.realview.ide.disks = [self.cf0]
- except:
+ elif hasattr(self.realview, "cf_ctrl"):
self.realview.cf_ctrl.disks = [self.cf0]
+ else:
+ self.pci_ide = IdeController(disks=[self.cf0])
+ pci_devices.append(self.pci_ide)
self.mem_ranges = []
size_remain = long(Addr(mdesc.mem()))
for region in self.realview._mem_regions:
- if size_remain > long(region[1]):
- self.mem_ranges.append(AddrRange(region[0], size=region[1]))
- size_remain = size_remain - long(region[1])
+ if size_remain > long(region.size()):
+ self.mem_ranges.append(region)
+ size_remain = size_remain - long(region.size())
else:
- self.mem_ranges.append(AddrRange(region[0], size=size_remain))
+ self.mem_ranges.append(AddrRange(region.start, size=size_remain))
size_remain = 0
break
warn("Memory size specified spans more than one region. Creating" \
" the amount of DRAM you've selected. Please try" \
" another platform")
+ self.have_security = security
+
if bare_metal:
# EOT character on UART will end the simulation
- self.realview.uart.end_on_eot = True
+ self.realview.uart[0].end_on_eot = True
else:
- if machine_type == "VExpress_EMM64":
- self.kernel = binary('vmlinux.aarch64.20140821')
- elif machine_type == "VExpress_EMM":
- self.kernel = binary('vmlinux.aarch32.ll_20131205.0-gem5')
- else:
- self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
-
if dtb_filename:
self.dtb_filename = binary(dtb_filename)
- self.machine_type = machine_type
+
+ self.machine_type = machine_type if machine_type in ArmMachineType.map \
+ else "DTOnly"
+
# Ensure that writes to the UART actually go out early in the boot
- boot_flags = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
- 'lpj=19988480 norandmaps rw loglevel=8 ' + \
- 'mem=%s root=/dev/sda1' % mdesc.mem()
+ if not cmdline:
+ cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
+ 'lpj=19988480 norandmaps rw loglevel=8 ' + \
+ 'mem=%(mem)s root=%(rootdev)s'
+
+ self.realview.setupBootLoader(self, binary)
+
+ if hasattr(self.realview.gic, 'cpu_addr'):
+ self.gic_cpu_addr = self.realview.gic.cpu_addr
- self.realview.setupBootLoader(self.membus, self, binary)
- self.gic_cpu_addr = self.realview.gic.cpu_addr
self.flags_addr = self.realview.realview_io.pio_addr + 0x30
- if mdesc.disk().lower().count('android'):
- boot_flags += " init=/init "
- self.boot_osflags = boot_flags
- self.realview.attachOnChipIO(self.membus, self.bridge)
- self.realview.attachIO(self.iobus)
+ # This check is for users who have previously put 'android' in
+ # the disk image filename to tell the config scripts to
+ # prepare the kernel with android-specific boot options. That
+ # behavior has been replaced with a more explicit option per
+ # the error message below. The disk can have any name now and
+ # doesn't need to include 'android' substring.
+ if (os.path.split(mdesc.disk())[-1]).lower().count('android'):
+ if 'android' not in mdesc.os_type():
+ fatal("It looks like you are trying to boot an Android " \
+ "platform. To boot Android, you must specify " \
+ "--os-type with an appropriate Android release on " \
+ "the command line.")
+
+ # android-specific tweaks
+ if 'android' in mdesc.os_type():
+ # generic tweaks
+ cmdline += " init=/init"
+
+ # release-specific tweaks
+ if 'kitkat' in mdesc.os_type():
+ cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
+ "android.bootanim=0 "
+ elif 'nougat' in mdesc.os_type():
+ cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
+ "android.bootanim=0 " + \
+ "vmalloc=640MB " + \
+ "android.early.fstab=/fstab.gem5 " + \
+ "androidboot.selinux=permissive " + \
+ "video=Virtual-1:1920x1080-16"
+
+ self.boot_osflags = fillInCmdline(mdesc, cmdline)
+
+ if external_memory:
+ # I/O traffic enters iobus
+ self.external_io = ExternalMaster(port_data="external_io",
+ port_type=external_memory)
+ self.external_io.port = self.iobus.slave
+
+ # Ensure iocache only receives traffic destined for (actual) memory.
+ self.iocache = ExternalSlave(port_data="iocache",
+ port_type=external_memory,
+ addr_ranges=self.mem_ranges)
+ self.iocache.port = self.iobus.master
+
+ # Let system_port get to nvmem and nothing else.
+ self.bridge.ranges = [self.realview.nvmem.range]
+
+ self.realview.attachOnChipIO(self.iobus)
+ # Attach off-chip devices
+ self.realview.attachIO(self.iobus)
+ elif ruby:
+ self._dma_ports = [ ]
+ self._mem_ports = [ ]
+ self.realview.attachOnChipIO(self.iobus,
+ dma_ports=self._dma_ports, mem_ports=self._mem_ports)
+ self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
+ else:
+ self.realview.attachOnChipIO(self.membus, self.bridge)
+ # Attach off-chip devices
+ self.realview.attachIO(self.iobus)
+
+ for dev_id, dev in enumerate(pci_devices):
+ dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0)
+ self.realview.attachPciDevice(
+ dev, self.iobus,
+ dma_ports=self._dma_ports if ruby else None)
+
self.intrctrl = IntrControl()
self.terminal = Terminal()
self.vncserver = VncServer()
- self.system_port = self.membus.slave
+ if not ruby:
+ self.system_port = self.membus.slave
+
+ if ruby:
+ if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1:
+ fatal("The MI_example protocol cannot implement Load/Store "
+ "Exclusive operations. Multicore ARM systems configured "
+ "with the MI_example protocol will not work properly.")
+ warn("You are trying to use Ruby on ARM, which is not working "
+ "properly yet.")
return self
-def makeLinuxMipsSystem(mem_mode, mdesc = None):
+def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
class BaseMalta(Malta):
ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
# generic system
mdesc = SysConfig()
self.readfile = mdesc.script()
- self.iobus = NoncoherentXBar()
+ self.iobus = IOXBar()
self.membus = MemBus()
self.bridge = Bridge(delay='50ns')
self.mem_ranges = [AddrRange('1GB')]
self.malta = BaseMalta()
self.malta.attachIO(self.iobus)
self.malta.ide.pio = self.iobus.master
- self.malta.ide.config = self.iobus.master
self.malta.ide.dma = self.iobus.slave
self.malta.ethernet.pio = self.iobus.master
- self.malta.ethernet.config = self.iobus.master
self.malta.ethernet.dma = self.iobus.slave
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
self.mem_mode = mem_mode
self.terminal = Terminal()
- self.kernel = binary('mips/vmlinux')
self.console = binary('mips/console')
- self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
+ if not cmdline:
+ cmdline = 'root=/dev/hda1 console=ttyS0'
+ self.boot_osflags = fillInCmdline(mdesc, cmdline)
self.system_port = self.membus.slave
x86_sys.membus = MemBus()
# North Bridge
- x86_sys.iobus = NoncoherentXBar()
+ x86_sys.iobus = IOXBar()
x86_sys.bridge = Bridge(delay='50ns')
x86_sys.bridge.master = x86_sys.iobus.slave
x86_sys.bridge.slave = x86_sys.membus.master
def connectX86RubySystem(x86_sys):
# North Bridge
- x86_sys.iobus = NoncoherentXBar()
+ x86_sys.iobus = IOXBar()
# add the ide to the list of dma devices that later need to attach to
# dma controllers
x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
-def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
- Ruby = False):
+def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False):
if self == None:
self = X86System()
# Set up the Intel MP table
base_entries = []
ext_entries = []
- for i in xrange(numCPUs):
+ for i in range(numCPUs):
bp = X86IntelMPProcessor(
local_apic_id = i,
local_apic_version = 0x14,
# In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
# but linux kernel cannot config PCI device if it was not connected to PCI bus,
# so we fix PCI bus id to 0, and ISA bus id to 1.
- pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI')
+ pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
base_entries.append(pci_bus)
- isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA')
+ isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
base_entries.append(isa_bus)
connect_busses = X86IntelMPBusHierarchy(bus_id=1,
subtractive_decode=True, parent_bus=0)
self.intel_mp_table.base_entries = base_entries
self.intel_mp_table.ext_entries = ext_entries
-def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None,
- Ruby = False):
+def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
+ cmdline=None):
self = LinuxX86System()
# Build up the x86 system and then specialize it for Linux
self.e820_table.entries = entries
# Command line
- self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
- 'root=/dev/hda1'
- self.kernel = binary('x86_64-vmlinux-2.6.22.9')
+ if not cmdline:
+ cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
+ self.boot_osflags = fillInCmdline(mdesc, cmdline)
return self
self.etherlink.dump = Parent.etherdump
return self
+
+
+def makeDistRoot(testSystem,
+ rank,
+ size,
+ server_name,
+ server_port,
+ sync_repeat,
+ sync_start,
+ linkspeed,
+ linkdelay,
+ dumpfile):
+ self = Root(full_system = True)
+ self.testsys = testSystem
+
+ self.etherlink = DistEtherLink(speed = linkspeed,
+ delay = linkdelay,
+ dist_rank = rank,
+ dist_size = size,
+ server_name = server_name,
+ server_port = server_port,
+ sync_start = sync_start,
+ sync_repeat = sync_repeat)
+
+ if hasattr(testSystem, 'realview'):
+ self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
+ elif hasattr(testSystem, 'tsunami'):
+ self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
+ else:
+ fatal("Don't know how to connect DistEtherLink to this system")
+
+ if dumpfile:
+ self.etherdump = EtherDump(file=dumpfile)
+ self.etherlink.dump = Parent.etherdump
+
+ return self
projects / gem5.git / blobdiff