-# Copyright (c) 2010-2012 ARM Limited
+# Copyright (c) 2010-2012, 2015-2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
#
# Authors: Kevin Lim
+from __future__ import print_function
+from __future__ import absolute_import
+
from m5.objects import *
-from Benchmarks import *
-from m5.util import convert
+from m5.util import *
+from .Benchmarks import *
+from . import ObjectList
+
+# Populate to reflect supported os types per target ISA
+os_types = { 'alpha' : [ 'linux' ],
+ 'mips' : [ 'linux' ],
+ 'sparc' : [ 'linux' ],
+ 'x86' : [ 'linux' ],
+ 'arm' : [ 'linux',
+ 'android-gingerbread',
+ 'android-ics',
+ 'android-jellybean',
+ 'android-kitkat',
+ 'android-nougat', ],
+ }
class CowIdeDisk(IdeDisk):
image = CowDiskImage(child=RawDiskImage(read_only=True),
def childImage(self, ci):
self.image.child.image_file = ci
-class MemBus(Bus):
+class MemBus(SystemXBar):
badaddr_responder = BadAddr()
default = Self.badaddr_responder.pio
+def fillInCmdline(mdesc, template, **kwargs):
+ kwargs.setdefault('disk', mdesc.disk())
+ kwargs.setdefault('rootdev', mdesc.rootdev())
+ kwargs.setdefault('mem', mdesc.mem())
+ kwargs.setdefault('script', mdesc.script())
+ return template % kwargs
+
+def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None):
-def makeLinuxAlphaSystem(mem_mode, mdesc = None):
- IO_address_space_base = 0x80000000000
class BaseTsunami(Tsunami):
ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
# generic system
mdesc = SysConfig()
self.readfile = mdesc.script()
- self.iobus = Bus(bus_id=0)
- self.membus = MemBus(bus_id=1)
- # By default the bridge responds to all addresses above the I/O
- # base address (including the PCI config space)
- self.bridge = Bridge(delay='50ns', nack_delay='4ns',
- ranges = [AddrRange(IO_address_space_base, Addr.max)])
- self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
- self.bridge.master = self.iobus.slave
- self.bridge.slave = self.membus.master
- self.physmem.port = self.membus.master
- self.disk0 = CowIdeDisk(driveID='master')
- self.disk2 = CowIdeDisk(driveID='master')
- self.disk0.childImage(mdesc.disk())
- self.disk2.childImage(disk('linux-bigswap2.img'))
+
self.tsunami = BaseTsunami()
+
+ # Create the io bus to connect all device ports
+ self.iobus = IOXBar()
self.tsunami.attachIO(self.iobus)
+
self.tsunami.ide.pio = self.iobus.master
- self.tsunami.ide.config = self.iobus.master
- self.tsunami.ide.dma = self.iobus.slave
- self.tsunami.ethernet.pio = self.iobus.master
- self.tsunami.ethernet.config = self.iobus.master
- self.tsunami.ethernet.dma = self.iobus.slave
- self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
- read_only = True))
- self.intrctrl = IntrControl()
- self.mem_mode = mem_mode
- self.terminal = Terminal()
- self.kernel = binary('vmlinux')
- self.pal = binary('ts_osfpal')
- self.console = binary('console')
- self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
- self.system_port = self.membus.slave
+ self.tsunami.ethernet.pio = self.iobus.master
- return self
+ if ruby:
+ # Store the dma devices for later connection to dma ruby ports.
+ # Append an underscore to dma_ports to avoid the SimObjectVector check.
+ self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
+ else:
+ self.membus = MemBus()
-def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
- class BaseTsunami(Tsunami):
- ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
- ide = IdeController(disks=[Parent.disk0, Parent.disk2],
- pci_func=0, pci_dev=0, pci_bus=0)
-
- physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
- self = LinuxAlphaSystem(physmem = physmem)
- if not mdesc:
- # generic system
- mdesc = SysConfig()
- self.readfile = mdesc.script()
+ # By default the bridge responds to all addresses above the I/O
+ # base address (including the PCI config space)
+ IO_address_space_base = 0x80000000000
+ self.bridge = Bridge(delay='50ns',
+ ranges = [AddrRange(IO_address_space_base, Addr.max)])
+ self.bridge.master = self.iobus.slave
+ self.bridge.slave = self.membus.master
- # Create pio bus to connect all device pio ports to rubymem's pio port
- self.piobus = Bus(bus_id=0)
+ self.tsunami.ide.dma = self.iobus.slave
+ self.tsunami.ethernet.dma = self.iobus.slave
- #
- # Pio functional accesses from devices need direct access to memory
- # RubyPort currently does support functional accesses. Therefore provide
- # the piobus a direct connection to physical memory
- #
- self.piobus.master = physmem.port
+ self.system_port = self.membus.slave
+ self.mem_ranges = [AddrRange(mdesc.mem())]
self.disk0 = CowIdeDisk(driveID='master')
self.disk2 = CowIdeDisk(driveID='master')
self.disk0.childImage(mdesc.disk())
self.disk2.childImage(disk('linux-bigswap2.img'))
- self.tsunami = BaseTsunami()
- self.tsunami.attachIO(self.piobus)
- self.tsunami.ide.pio = self.piobus.master
- self.tsunami.ide.config = self.piobus.master
- self.tsunami.ethernet.pio = self.piobus.master
- self.tsunami.ethernet.config = self.piobus.master
-
- #
- # Store the dma devices for later connection to dma ruby ports.
- # Append an underscore to dma_devices to avoid the SimObjectVector check.
- #
- self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
-
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
self.mem_mode = mem_mode
self.terminal = Terminal()
- self.kernel = binary('vmlinux')
self.pal = binary('ts_osfpal')
self.console = binary('console')
- self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
+ if not cmdline:
+ cmdline = 'root=/dev/hda1 console=ttyS0'
+ self.boot_osflags = fillInCmdline(mdesc, cmdline)
return self
-def makeSparcSystem(mem_mode, mdesc = None):
+def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
# Constants from iob.cc and uart8250.cc
iob_man_addr = 0x9800000000
uart_pio_size = 8
# generic system
mdesc = SysConfig()
self.readfile = mdesc.script()
- self.iobus = Bus(bus_id=0)
- self.membus = MemBus(bus_id=1)
- self.bridge = Bridge(delay='50ns', nack_delay='4ns')
+ self.iobus = IOXBar()
+ self.membus = MemBus()
+ self.bridge = Bridge(delay='50ns')
self.t1000 = T1000()
self.t1000.attachOnChipIO(self.membus)
self.t1000.attachIO(self.iobus)
- self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
- self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
+ self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
+ AddrRange(Addr('2GB'), size ='256MB')]
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
- self.physmem.port = self.membus.master
- self.physmem2.port = self.membus.master
self.rom.port = self.membus.master
self.nvram.port = self.membus.master
self.hypervisor_desc.port = self.membus.master
self.partition_desc.port = self.membus.master
self.intrctrl = IntrControl()
self.disk0 = CowMmDisk()
- self.disk0.childImage(disk('disk.s10hw2'))
+ self.disk0.childImage(mdesc.disk())
self.disk0.pio = self.iobus.master
# The puart0 and hvuart are placed on the IO bus, so create ranges
return self
-def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
+def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
+ dtb_filename=None, bare_metal=False, cmdline=None,
+ external_memory="", ruby=False, security=False):
assert machine_type
+ pci_devices = []
+
if bare_metal:
self = ArmSystem()
else:
mdesc = SysConfig()
self.readfile = mdesc.script()
- self.iobus = Bus(bus_id=0)
- self.membus = MemBus(bus_id=1)
- self.membus.badaddr_responder.warn_access = "warn"
- self.bridge = Bridge(delay='50ns', nack_delay='4ns')
- self.bridge.master = self.iobus.slave
- self.bridge.slave = self.membus.master
+ self.iobus = IOXBar()
+ if not ruby:
+ self.bridge = Bridge(delay='50ns')
+ self.bridge.master = self.iobus.slave
+ self.membus = MemBus()
+ self.membus.badaddr_responder.warn_access = "warn"
+ self.bridge.slave = self.membus.master
self.mem_mode = mem_mode
- if machine_type == "RealView_PBX":
- self.realview = RealViewPBX()
- elif machine_type == "RealView_EB":
- self.realview = RealViewEB()
- elif machine_type == "VExpress_ELT":
- self.realview = VExpress_ELT()
- elif machine_type == "VExpress_EMM":
- self.realview = VExpress_EMM()
- self.load_addr_mask = 0xffffffff
- else:
- print "Unknown Machine Type"
- sys.exit(1)
+ platform_class = ObjectList.platform_list.get(machine_type)
+ # Resolve the real platform name, the original machine_type
+ # variable might have been an alias.
+ machine_type = platform_class.__name__
+ self.realview = platform_class()
+ self._bootmem = self.realview.bootmem
+
+ if isinstance(self.realview, VExpress_EMM64):
+ if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img':
+ print("Selected 64-bit ARM architecture, updating default "
+ "disk image...")
+ mdesc.diskname = 'linaro-minimal-aarch64.img'
+
+
+ # Attach any PCI devices this platform supports
+ self.realview.attachPciDevices()
self.cf0 = CowIdeDisk(driveID='master')
self.cf0.childImage(mdesc.disk())
- # default to an IDE controller rather than a CF one
- # assuming we've got one
- try:
+ # Old platforms have a built-in IDE or CF controller. Default to
+ # the IDE controller if both exist. New platforms expect the
+ # storage controller to be added from the config script.
+ if hasattr(self.realview, "ide"):
self.realview.ide.disks = [self.cf0]
- except:
+ elif hasattr(self.realview, "cf_ctrl"):
self.realview.cf_ctrl.disks = [self.cf0]
+ else:
+ self.pci_ide = IdeController(disks=[self.cf0])
+ pci_devices.append(self.pci_ide)
+
+ self.mem_ranges = []
+ size_remain = long(Addr(mdesc.mem()))
+ for region in self.realview._mem_regions:
+ if size_remain > long(region.size()):
+ self.mem_ranges.append(region)
+ size_remain = size_remain - long(region.size())
+ else:
+ self.mem_ranges.append(AddrRange(region.start, size=size_remain))
+ size_remain = 0
+ break
+ warn("Memory size specified spans more than one region. Creating" \
+ " another memory controller for that range.")
+
+ if size_remain > 0:
+ fatal("The currently selected ARM platforms doesn't support" \
+ " the amount of DRAM you've selected. Please try" \
+ " another platform")
+
+ self.have_security = security
if bare_metal:
# EOT character on UART will end the simulation
- self.realview.uart.end_on_eot = True
- self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())),
- zero = True)
+ self.realview.uart[0].end_on_eot = True
else:
- self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
- self.machine_type = machine_type
- if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
- print "The currently selected ARM platforms doesn't support"
- print " the amount of DRAM you've selected. Please try"
- print " another platform"
- sys.exit(1)
-
- boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
- 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
-
- self.physmem = PhysicalMemory(range = AddrRange(self.realview.mem_start_addr,
- size = mdesc.mem()))
- self.realview.setupBootLoader(self.membus, self, binary)
- self.gic_cpu_addr = self.realview.gic.cpu_addr
+ if dtb_filename:
+ self.dtb_filename = binary(dtb_filename)
+
+ self.machine_type = machine_type if machine_type in ArmMachineType.map \
+ else "DTOnly"
+
+ # Ensure that writes to the UART actually go out early in the boot
+ if not cmdline:
+ cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
+ 'lpj=19988480 norandmaps rw loglevel=8 ' + \
+ 'mem=%(mem)s root=%(rootdev)s'
+
+ self.realview.setupBootLoader(self, binary)
+
+ if hasattr(self.realview.gic, 'cpu_addr'):
+ self.gic_cpu_addr = self.realview.gic.cpu_addr
+
self.flags_addr = self.realview.realview_io.pio_addr + 0x30
- if mdesc.disk().lower().count('android'):
- boot_flags += " init=/init "
- self.boot_osflags = boot_flags
+ # This check is for users who have previously put 'android' in
+ # the disk image filename to tell the config scripts to
+ # prepare the kernel with android-specific boot options. That
+ # behavior has been replaced with a more explicit option per
+ # the error message below. The disk can have any name now and
+ # doesn't need to include 'android' substring.
+ if (os.path.split(mdesc.disk())[-1]).lower().count('android'):
+ if 'android' not in mdesc.os_type():
+ fatal("It looks like you are trying to boot an Android " \
+ "platform. To boot Android, you must specify " \
+ "--os-type with an appropriate Android release on " \
+ "the command line.")
+
+ # android-specific tweaks
+ if 'android' in mdesc.os_type():
+ # generic tweaks
+ cmdline += " init=/init"
+
+ # release-specific tweaks
+ if 'kitkat' in mdesc.os_type():
+ cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
+ "android.bootanim=0 "
+ elif 'nougat' in mdesc.os_type():
+ cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
+ "android.bootanim=0 " + \
+ "vmalloc=640MB " + \
+ "android.early.fstab=/fstab.gem5 " + \
+ "androidboot.selinux=permissive " + \
+ "video=Virtual-1:1920x1080-16"
+
+ self.boot_osflags = fillInCmdline(mdesc, cmdline)
+
+ if external_memory:
+ # I/O traffic enters iobus
+ self.external_io = ExternalMaster(port_data="external_io",
+ port_type=external_memory)
+ self.external_io.port = self.iobus.slave
+
+ # Ensure iocache only receives traffic destined for (actual) memory.
+ self.iocache = ExternalSlave(port_data="iocache",
+ port_type=external_memory,
+ addr_ranges=self.mem_ranges)
+ self.iocache.port = self.iobus.master
+
+ # Let system_port get to nvmem and nothing else.
+ self.bridge.ranges = [self.realview.nvmem.range]
+
+ self.realview.attachOnChipIO(self.iobus)
+ # Attach off-chip devices
+ self.realview.attachIO(self.iobus)
+ elif ruby:
+ self._dma_ports = [ ]
+ self._mem_ports = [ ]
+ self.realview.attachOnChipIO(self.iobus,
+ dma_ports=self._dma_ports, mem_ports=self._mem_ports)
+ self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
+ else:
+ self.realview.attachOnChipIO(self.membus, self.bridge)
+ # Attach off-chip devices
+ self.realview.attachIO(self.iobus)
+
+ for dev_id, dev in enumerate(pci_devices):
+ dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0)
+ self.realview.attachPciDevice(
+ dev, self.iobus,
+ dma_ports=self._dma_ports if ruby else None)
- self.physmem.port = self.membus.master
- self.realview.attachOnChipIO(self.membus, self.bridge)
- self.realview.attachIO(self.iobus)
self.intrctrl = IntrControl()
self.terminal = Terminal()
self.vncserver = VncServer()
- self.system_port = self.membus.slave
+ if not ruby:
+ self.system_port = self.membus.slave
+
+ if ruby:
+ if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1:
+ fatal("The MI_example protocol cannot implement Load/Store "
+ "Exclusive operations. Multicore ARM systems configured "
+ "with the MI_example protocol will not work properly.")
+ warn("You are trying to use Ruby on ARM, which is not working "
+ "properly yet.")
return self
-def makeLinuxMipsSystem(mem_mode, mdesc = None):
+def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
class BaseMalta(Malta):
ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
# generic system
mdesc = SysConfig()
self.readfile = mdesc.script()
- self.iobus = Bus(bus_id=0)
- self.membus = MemBus(bus_id=1)
- self.bridge = Bridge(delay='50ns', nack_delay='4ns')
- self.physmem = PhysicalMemory(range = AddrRange('1GB'))
+ self.iobus = IOXBar()
+ self.membus = MemBus()
+ self.bridge = Bridge(delay='50ns')
+ self.mem_ranges = [AddrRange('1GB')]
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
- self.physmem.port = self.membus.master
self.disk0 = CowIdeDisk(driveID='master')
self.disk2 = CowIdeDisk(driveID='master')
self.disk0.childImage(mdesc.disk())
self.malta = BaseMalta()
self.malta.attachIO(self.iobus)
self.malta.ide.pio = self.iobus.master
- self.malta.ide.config = self.iobus.master
self.malta.ide.dma = self.iobus.slave
self.malta.ethernet.pio = self.iobus.master
- self.malta.ethernet.config = self.iobus.master
self.malta.ethernet.dma = self.iobus.slave
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
self.mem_mode = mem_mode
self.terminal = Terminal()
- self.kernel = binary('mips/vmlinux')
self.console = binary('mips/console')
- self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
+ if not cmdline:
+ cmdline = 'root=/dev/hda1 console=ttyS0'
+ self.boot_osflags = fillInCmdline(mdesc, cmdline)
self.system_port = self.membus.slave
interrupts_address_space_base = 0xa000000000000000
APIC_range_size = 1 << 12;
- x86_sys.membus = MemBus(bus_id=1)
- x86_sys.physmem.port = x86_sys.membus.master
+ x86_sys.membus = MemBus()
# North Bridge
- x86_sys.iobus = Bus(bus_id=0)
- x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
+ x86_sys.iobus = IOXBar()
+ x86_sys.bridge = Bridge(delay='50ns')
x86_sys.bridge.master = x86_sys.iobus.slave
x86_sys.bridge.slave = x86_sys.membus.master
- # Allow the bridge to pass through the IO APIC (two pages),
- # everything in the IO address range up to the local APIC, and
- # then the entire PCI address space and beyond
+ # Allow the bridge to pass through:
+ # 1) kernel configured PCI device memory map address: address range
+ # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
+ # 2) the bridge to pass through the IO APIC (two pages, already contained in 1),
+ # 3) everything in the IO address range up to the local APIC, and
+ # 4) then the entire PCI address space and beyond.
x86_sys.bridge.ranges = \
[
- AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
- x86_sys.pc.south_bridge.io_apic.pio_addr +
- APIC_range_size - 1),
+ AddrRange(0xC0000000, 0xFFFF0000),
AddrRange(IO_address_space_base,
interrupts_address_space_base - 1),
AddrRange(pci_config_address_space_base,
# Create a bridge from the IO bus to the memory bus to allow access to
# the local APIC (two pages)
- x86_sys.apicbridge = Bridge(delay='50ns', nack_delay='4ns')
+ x86_sys.apicbridge = Bridge(delay='50ns')
x86_sys.apicbridge.slave = x86_sys.iobus.master
x86_sys.apicbridge.master = x86_sys.membus.slave
x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
def connectX86RubySystem(x86_sys):
# North Bridge
- x86_sys.piobus = Bus(bus_id=0)
-
- #
- # Pio functional accesses from devices need direct access to memory
- # RubyPort currently does support functional accesses. Therefore provide
- # the piobus a direct connection to physical memory
- #
- x86_sys.piobus.master = x86_sys.physmem.port
+ x86_sys.iobus = IOXBar()
+
# add the ide to the list of dma devices that later need to attach to
# dma controllers
x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
- x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
+ x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
-def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
+def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False):
if self == None:
self = X86System()
self.mem_mode = mem_mode
# Physical memory
- self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
+ # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
+ # for various devices. Hence, if the physical memory size is greater than
+ # 3GB, we need to split it into two parts.
+ excess_mem_size = \
+ convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
+ if excess_mem_size <= 0:
+ self.mem_ranges = [AddrRange(mdesc.mem())]
+ else:
+ warn("Physical memory size specified is %s which is greater than " \
+ "3GB. Twice the number of memory controllers would be " \
+ "created." % (mdesc.mem()))
+
+ self.mem_ranges = [AddrRange('3GB'),
+ AddrRange(Addr('4GB'), size = excess_mem_size)]
# Platform
self.pc = Pc()
# Set up the Intel MP table
base_entries = []
ext_entries = []
- for i in xrange(numCPUs):
+ for i in range(numCPUs):
bp = X86IntelMPProcessor(
local_apic_id = i,
local_apic_version = 0x14,
address = 0xfec00000)
self.pc.south_bridge.io_apic.apic_id = io_apic.id
base_entries.append(io_apic)
- isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
- base_entries.append(isa_bus)
- pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
+ # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
+ # but linux kernel cannot config PCI device if it was not connected to PCI bus,
+ # so we fix PCI bus id to 0, and ISA bus id to 1.
+ pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
base_entries.append(pci_bus)
- connect_busses = X86IntelMPBusHierarchy(bus_id=0,
- subtractive_decode=True, parent_bus=1)
+ isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
+ base_entries.append(isa_bus)
+ connect_busses = X86IntelMPBusHierarchy(bus_id=1,
+ subtractive_decode=True, parent_bus=0)
ext_entries.append(connect_busses)
pci_dev4_inta = X86IntelMPIOIntAssignment(
interrupt_type = 'INT',
polarity = 'ConformPolarity',
trigger = 'ConformTrigger',
- source_bus_id = 1,
+ source_bus_id = 0,
source_bus_irq = 0 + (4 << 2),
dest_io_apic_id = io_apic.id,
dest_io_apic_intin = 16)
interrupt_type = 'ExtInt',
polarity = 'ConformPolarity',
trigger = 'ConformTrigger',
- source_bus_id = 0,
+ source_bus_id = 1,
source_bus_irq = irq,
dest_io_apic_id = io_apic.id,
dest_io_apic_intin = 0)
interrupt_type = 'INT',
polarity = 'ConformPolarity',
trigger = 'ConformTrigger',
- source_bus_id = 0,
+ source_bus_id = 1,
source_bus_irq = irq,
dest_io_apic_id = io_apic.id,
dest_io_apic_intin = apicPin)
self.intel_mp_table.base_entries = base_entries
self.intel_mp_table.ext_entries = ext_entries
-def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
+def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
+ cmdline=None):
self = LinuxX86System()
# Build up the x86 system and then specialize it for Linux
# We assume below that there's at least 1MB of memory. We'll require 2
# just to avoid corner cases.
- assert(self.physmem.range.second.getValue() >= 0x200000)
+ phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
+ assert(phys_mem_size >= 0x200000)
+ assert(len(self.mem_ranges) <= 2)
- self.e820_table.entries = \
+ entries = \
[
# Mark the first megabyte of memory as reserved
- X86E820Entry(addr = 0, size = '1MB', range_type = 2),
- # Mark the rest as available
+ X86E820Entry(addr = 0, size = '639kB', range_type = 1),
+ X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
+ # Mark the rest of physical memory as available
X86E820Entry(addr = 0x100000,
- size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
- range_type = 1)
+ size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
+ range_type = 1),
]
+ # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
+ # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
+ # specific range can pass though bridge to iobus.
+ if len(self.mem_ranges) == 1:
+ entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
+ size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
+ range_type=2))
+
+ # Reserve the last 16kB of the 32-bit address space for the m5op interface
+ entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
+
+ # In case the physical memory is greater than 3GB, we split it into two
+ # parts and add a separate e820 entry for the second part. This entry
+ # starts at 0x100000000, which is the first address after the space
+ # reserved for devices.
+ if len(self.mem_ranges) == 2:
+ entries.append(X86E820Entry(addr = 0x100000000,
+ size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
+
+ self.e820_table.entries = entries
+
# Command line
- self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
- 'root=/dev/hda1'
+ if not cmdline:
+ cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
+ self.boot_osflags = fillInCmdline(mdesc, cmdline)
return self
self.testsys = testSystem
self.drivesys = driveSystem
self.etherlink = EtherLink()
- self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
- self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
if hasattr(testSystem, 'realview'):
self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
return self
-def setMipsOptions(TestCPUClass):
- #CP0 Configuration
- TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
- TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
- TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
- TestCPUClass.CoreParams.CP0_PRId_Revision = 0
-
- #CP0 Interrupt Control
- TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
- TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
-
- # Config Register
- #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
- #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
- TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
- TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
- TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
- TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
- #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
-
- #Config 1 Register
- TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
- TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
- # ***VERY IMPORTANT***
- # Remember to modify CP0_Config1 according to cache specs
- # Examine file ../common/Cache.py
- TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
- TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
- TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
- TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
- TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
- TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
- TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
- TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
- TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
- TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
- TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
- TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
- TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
-
- #Config 2 Register
- TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
- TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
- TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
- TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
- TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
- TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
- TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
- TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
- TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
-
-
- #Config 3 Register
- TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
- TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
- TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
- TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
- TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
- TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
- TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
- TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
- TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
-
- #SRS Ctl - HSS
- TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
-
-
- #TestCPUClass.CoreParams.tlb = TLB()
- #TestCPUClass.CoreParams.UnifiedTLB = 1
+
+def makeDistRoot(testSystem,
+ rank,
+ size,
+ server_name,
+ server_port,
+ sync_repeat,
+ sync_start,
+ linkspeed,
+ linkdelay,
+ dumpfile):
+ self = Root(full_system = True)
+ self.testsys = testSystem
+
+ self.etherlink = DistEtherLink(speed = linkspeed,
+ delay = linkdelay,
+ dist_rank = rank,
+ dist_size = size,
+ server_name = server_name,
+ server_port = server_port,
+ sync_start = sync_start,
+ sync_repeat = sync_repeat)
+
+ if hasattr(testSystem, 'realview'):
+ self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
+ elif hasattr(testSystem, 'tsunami'):
+ self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
+ else:
+ fatal("Don't know how to connect DistEtherLink to this system")
+
+ if dumpfile:
+ self.etherdump = EtherDump(file=dumpfile)
+ self.etherlink.dump = Parent.etherdump
+
+ return self
projects / gem5.git / blobdiff