DMA: Add IOCache and fix bus bridge to optionally only send requests one

[gem5.git] / configs / common / Simulation.py

diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index afa147537da5c62f0ea1242cef4edb2d5c1173bf..61b14f0266c311534387f2002a25ceb5f600ebeb 100644 (file)
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -39,6 +39,9 @@ def setCPUClass(options):
     if options.timing:
         TmpClass = TimingSimpleCPU
     elif options.detailed:
+        if not options.caches:
+            print "O3 CPU must be used with caches"
+            sys.exit(1)
         TmpClass = DerivO3CPU
     else:
         TmpClass = AtomicSimpleCPU
@@ -61,11 +64,11 @@ def run(options, root, testsys, cpu_class):
     if options.maxtick:
         maxtick = options.maxtick
     elif options.maxtime:
-        simtime = int(options.maxtime * root.clock.value)
+        simtime = m5.ticks.seconds(simtime)
         print "simulating for: ", simtime
         maxtick = simtime
     else:
-        maxtick = -1
+        maxtick = m5.MaxTick
 
     if options.checkpoint_dir:
         cptdir = options.checkpoint_dir
@@ -85,10 +88,6 @@ def run(options, root, testsys, cpu_class):
             if not m5.build_env['FULL_SYSTEM']:
                 switch_cpus[i].workload = testsys.cpu[i].workload
             switch_cpus[i].clock = testsys.cpu[0].clock
-            if options.caches:
-                switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
-                                                       L1Cache(size = '64kB'))
-                switch_cpus[i].connectMemPorts(testsys.membus)
 
         root.switch_cpus = switch_cpus
         switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
@@ -108,19 +107,15 @@ def run(options, root, testsys, cpu_class):
             switch_cpus[i].clock = testsys.cpu[0].clock
             switch_cpus_1[i].clock = testsys.cpu[0].clock
 
-            if options.caches:
-                switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
-                                                       L1Cache(size = '64kB'))
-                switch_cpus[i].connectMemPorts(testsys.membus)
-            else:
+            if not options.caches:
                 # O3 CPU must have a cache to work.
                 switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
                                                          L1Cache(size = '64kB'))
                 switch_cpus_1[i].connectMemPorts(testsys.membus)
 
 
-            root.switch_cpus = switch_cpus
-            root.switch_cpus_1 = switch_cpus_1
+            testsys.switch_cpus = switch_cpus
+            testsys.switch_cpus_1 = switch_cpus_1
             switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
             switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
 
@@ -149,6 +144,10 @@ def run(options, root, testsys, cpu_class):
         if cpt_num > len(cpts):
             m5.panic('Checkpoint %d not found' % cpt_num)
 
+        ## Adjust max tick based on our starting tick
+        maxtick = maxtick - int(cpts[cpt_num - 1])
+
+        ## Restore the checkpoint
         m5.restoreCheckpoint(root,
                              joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]))
 
@@ -190,8 +189,9 @@ def run(options, root, testsys, cpu_class):
 
         sim_ticks = when
         exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
-        while num_checkpoints < max_checkpoints:
-            if (sim_ticks + period) > maxtick and maxtick != -1:
+        while num_checkpoints < max_checkpoints and \
+                exit_event.getCause() != "user interrupt received":
+            if (sim_ticks + period) > maxtick:
                 exit_event = m5.simulate(maxtick - sim_ticks)
                 exit_cause = exit_event.getCause()
                 break
@@ -204,6 +204,10 @@ def run(options, root, testsys, cpu_class):
                     m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
                     num_checkpoints += 1
 
+        if exit_event.getCause() == "user interrupt received":
+            exit_cause = exit_event.getCause();
+
+
     else: #no checkpoints being taken via this script
         exit_event = m5.simulate(maxtick)
 
@@ -214,14 +218,10 @@ def run(options, root, testsys, cpu_class):
                 exit_cause =  "maximum %d checkpoints dropped" % max_checkpoints
                 break
 
-            if maxtick == -1:
-                exit_event = m5.simulate(maxtick)
-            else:
-                exit_event = m5.simulate(maxtick - m5.curTick())
-
+            exit_event = m5.simulate(maxtick - m5.curTick())
             exit_cause = exit_event.getCause()
 
     if exit_cause == '':
         exit_cause = exit_event.getCause()
-    print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause
+    print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause)