-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# Authors: Lisa Hsu
from os import getcwd
+from os.path import join as joinpath
import m5
from m5.objects import *
m5.AddToPath('../common')
from Caches import L1Cache
-def run(options, root, testsys):
+def setCPUClass(options):
+
+ atomic = False
+ if options.timing:
+ TmpClass = TimingSimpleCPU
+ elif options.detailed:
+ if not options.caches:
+ print "O3 CPU must be used with caches"
+ sys.exit(1)
+ TmpClass = DerivO3CPU
+ else:
+ TmpClass = AtomicSimpleCPU
+ atomic = True
+
+ CPUClass = None
+ test_mem_mode = 'atomic'
+
+ if not atomic:
+ if options.checkpoint_restore:
+ CPUClass = TmpClass
+ TmpClass = AtomicSimpleCPU
+ else:
+ test_mem_mode = 'timing'
+
+ return (TmpClass, test_mem_mode, CPUClass)
+
+
+def run(options, root, testsys, cpu_class):
if options.maxtick:
maxtick = options.maxtick
elif options.maxtime:
- simtime = int(options.maxtime * root.clock.value)
+ simtime = m5.ticks.seconds(simtime)
print "simulating for: ", simtime
maxtick = simtime
else:
- maxtick = -1
+ maxtick = m5.MaxTick
if options.checkpoint_dir:
cptdir = options.checkpoint_dir
np = options.num_cpus
max_checkpoints = options.max_checkpoints
+ switch_cpus = None
+
+ if cpu_class:
+ switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
+ for i in xrange(np)]
+
+ for i in xrange(np):
+ switch_cpus[i].system = testsys
+ if not m5.build_env['FULL_SYSTEM']:
+ switch_cpus[i].workload = testsys.cpu[i].workload
+ switch_cpus[i].clock = testsys.cpu[0].clock
+
+ root.switch_cpus = switch_cpus
+ switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
if options.standard_switch:
switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
for i in xrange(np)]
- switch_cpus1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
+ switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
for i in xrange(np)]
+
for i in xrange(np):
switch_cpus[i].system = testsys
- switch_cpus1[i].system = testsys
+ switch_cpus_1[i].system = testsys
if not m5.build_env['FULL_SYSTEM']:
switch_cpus[i].workload = testsys.cpu[i].workload
- switch_cpus1[i].workload = testsys.cpu[i].workload
+ switch_cpus_1[i].workload = testsys.cpu[i].workload
switch_cpus[i].clock = testsys.cpu[0].clock
- switch_cpus1[i].clock = testsys.cpu[0].clock
- if options.caches:
- switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
- L1Cache(size = '64kB'))
-
- switch_cpus[i].mem = testsys.physmem
- switch_cpus1[i].mem = testsys.physmem
- switch_cpus[i].connectMemPorts(testsys.membus)
- root.switch_cpus = switch_cpus
- root.switch_cpus1 = switch_cpus1
+ switch_cpus_1[i].clock = testsys.cpu[0].clock
+
+ if not options.caches:
+ # O3 CPU must have a cache to work.
+ switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
+ L1Cache(size = '64kB'))
+ switch_cpus_1[i].connectMemPorts(testsys.membus)
+
+
+ testsys.switch_cpus = switch_cpus
+ testsys.switch_cpus_1 = switch_cpus_1
switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
- switch_cpu_list1 = [(switch_cpus[i], switch_cpus1[i]) for i in xrange(np)]
+ switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
m5.instantiate(root)
m5.panic("checkpoint dir %s does not exist!" % cptdir)
dirs = listdir(cptdir)
- expr = re.compile('cpt.([0-9]*)')
+ expr = re.compile('cpt\.([0-9]*)')
cpts = []
for dir in dirs:
match = expr.match(dir)
if cpt_num > len(cpts):
m5.panic('Checkpoint %d not found' % cpt_num)
+ ## Adjust max tick based on our starting tick
+ maxtick = maxtick - int(cpts[cpt_num - 1])
+
+ ## Restore the checkpoint
m5.restoreCheckpoint(root,
- "/".join([cptdir, "cpt.%s" % cpts[cpt_num - 1]]))
+ joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]))
- if options.standard_switch:
+ if options.standard_switch or cpu_class:
exit_event = m5.simulate(10000)
## when you change to Timing (or Atomic), you halt the system given
m5.switchCpus(switch_cpu_list)
m5.resume(testsys)
- exit_event = m5.simulate(options.warmup)
- m5.switchCpus(switch_cpu_list1)
+ if options.standard_switch:
+ exit_event = m5.simulate(options.warmup)
+ m5.drain(testsys)
+ m5.switchCpus(switch_cpu_list1)
+ m5.resume(testsys)
num_checkpoints = 0
exit_cause = ''
exit_event = m5.simulate(when - m5.curTick())
if exit_event.getCause() == "simulate() limit reached":
- m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
+ m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
num_checkpoints += 1
sim_ticks = when
exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
- while num_checkpoints < max_checkpoints:
- if (sim_ticks + period) > maxtick and maxtick != -1:
+ while num_checkpoints < max_checkpoints and \
+ exit_event.getCause() != "user interrupt received":
+ if (sim_ticks + period) > maxtick:
exit_event = m5.simulate(maxtick - sim_ticks)
exit_cause = exit_event.getCause()
break
while exit_event.getCause() == "checkpoint":
exit_event = m5.simulate(sim_ticks - m5.curTick())
if exit_event.getCause() == "simulate() limit reached":
- m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
+ m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
num_checkpoints += 1
+ if exit_event.getCause() == "user interrupt received":
+ exit_cause = exit_event.getCause();
+
+
else: #no checkpoints being taken via this script
exit_event = m5.simulate(maxtick)
while exit_event.getCause() == "checkpoint":
- m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
+ m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
num_checkpoints += 1
if num_checkpoints == max_checkpoints:
exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
break
- if maxtick == -1:
- exit_event = m5.simulate(maxtick)
- else:
- exit_event = m5.simulate(maxtick - m5.curTick())
-
+ exit_event = m5.simulate(maxtick - m5.curTick())
exit_cause = exit_event.getCause()
if exit_cause == '':
exit_cause = exit_event.getCause()
- print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause
+ print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause)
projects / gem5.git / blobdiff