cpu: Fixed ratio of pred to hyst bits for LTAGE Bimodal

[gem5.git] / configs / dram / lat_mem_rd.py

diff --git a/configs/dram/lat_mem_rd.py b/configs/dram/lat_mem_rd.py
index 87917418d43ae71646693b1c3adab9734422f52b..dc80bd287a35c9a00bdb19cd2fbd3bad78d24049 100644 (file)
--- a/configs/dram/lat_mem_rd.py
+++ b/configs/dram/lat_mem_rd.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2015 ARM Limited
+# Copyright (c) 2015-2016 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -35,6 +35,8 @@
 #
 # Authors: Andreas Hansson
 
+from __future__ import print_function
+
 import gzip
 import optparse
 import os
@@ -42,10 +44,10 @@ import os
 import m5
 from m5.objects import *
 from m5.util import addToPath
-from m5.internal.stats import periodicStatDump
+from m5.stats import periodicStatDump
 
-addToPath('../common')
-import MemConfig
+addToPath('../')
+from common import MemConfig
 
 addToPath('../../util')
 import protolib
@@ -60,27 +62,27 @@ import protolib
 try:
     import packet_pb2
 except:
-    print "Did not find packet proto definitions, attempting to generate"
+    print("Did not find packet proto definitions, attempting to generate")
     from subprocess import call
     error = call(['protoc', '--python_out=configs/dram',
                   '--proto_path=src/proto', 'src/proto/packet.proto'])
     if not error:
-        print "Generated packet proto definitions"
+        print("Generated packet proto definitions")
 
         try:
             import google.protobuf
         except:
-            print "Please install the Python protobuf module"
+            print("Please install the Python protobuf module")
             exit(-1)
 
         import packet_pb2
     else:
-        print "Failed to import packet proto definitions"
+        print("Failed to import packet proto definitions")
         exit(-1)
 
 parser = optparse.OptionParser()
 
-parser.add_option("--mem-type", type="choice", default="DDR3_1600_x64",
+parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
                   choices=MemConfig.mem_names(),
                   help = "type of memory to use")
 parser.add_option("--mem-size", action="store", type="string",
@@ -92,7 +94,7 @@ parser.add_option("--reuse-trace", action="store_true",
 (options, args) = parser.parse_args()
 
 if args:
-    print "Error: script doesn't take any positional arguments"
+    print("Error: script doesn't take any positional arguments")
     sys.exit(1)
 
 # start by creating the system itself, using a multi-layer 2.0 GHz
@@ -171,7 +173,7 @@ def create_trace(filename, max_addr, burst_size, itt):
     try:
         proto_out = gzip.open(filename, 'wb')
     except IOError:
-        print "Failed to open ", filename, " for writing"
+        print("Failed to open ", filename, " for writing")
         exit(-1)
 
     # write the magic number in 4-byte Little Endian, similar to what
@@ -208,7 +210,7 @@ def create_trace(filename, max_addr, burst_size, itt):
     proto_out.close()
 
 # this will take a while, so keep the user informed
-print "Generating traces, please wait..."
+print("Generating traces, please wait...")
 
 nxt_range = 0
 nxt_state = 0
@@ -247,22 +249,26 @@ cfg_file.write("TRANSITION %d %d 1\n" % (nxt_state - 1, nxt_state - 1))
 cfg_file.close()
 
 # create a traffic generator, and point it to the file we just created
-system.tgen = TrafficGen(config_file = cfg_file_name)
+system.tgen = TrafficGen(config_file = cfg_file_name,
+                         progress_check = '10s')
 
 # add a communication monitor
 system.monitor = CommMonitor()
+system.monitor.footprint = MemFootprintProbe()
 
 # connect the traffic generator to the system
 system.tgen.port = system.monitor.slave
 
 # create the actual cache hierarchy, for now just go with something
 # basic to explore some of the options
-from Caches import *
+from common.Caches import *
 
 # a starting point for an L3 cache
 class L3Cache(Cache):
     assoc = 16
-    hit_latency = 40
+    tag_latency = 20
+    data_latency = 20
+    sequential_access = True
     response_latency = 40
     mshrs = 32
     tgts_per_mshr = 12
@@ -300,6 +306,6 @@ m5.instantiate()
 m5.simulate(nxt_state * period)
 
 # print all we need to make sense of the stats output
-print "lat_mem_rd with %d iterations, ranges:" % iterations
+print("lat_mem_rd with %d iterations, ranges:" % iterations)
 for r in ranges:
-    print r
+    print(r)