-# Copyright (c) 2014-2015 ARM Limited
+# Copyright (c) 2014-2015, 2018-2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Hansson
+import math
import optparse
import m5
from m5.objects import *
from m5.util import addToPath
-from m5.internal.stats import periodicStatDump
+from m5.stats import periodicStatDump
-addToPath('../common')
+addToPath('../')
-import MemConfig
+from common import ObjectList
+from common import MemConfig
# this script is helpful to sweep the efficiency of a specific memory
# controller configuration, by varying the number of banks accessed,
parser = optparse.OptionParser()
-# Use a single-channel DDR3-1600 x64 by default
-parser.add_option("--mem-type", type="choice", default="DDR3_1600_x64",
- choices=MemConfig.mem_names(),
+dram_generators = {
+ "DRAM" : lambda x: x.createDram,
+ "DRAM_ROTATE" : lambda x: x.createDramRot,
+}
+
+# Use a single-channel DDR3-1600 x64 (8x8 topology) by default
+parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
+ choices=ObjectList.mem_list.get_names(),
help = "type of memory to use")
parser.add_option("--mem-ranks", "-r", type="int", default=1,
help = "Percentage of read commands")
parser.add_option("--mode", type="choice", default="DRAM",
- choices=["DRAM", "DRAM_ROTATE"],
+ choices=list(dram_generators.keys()),
help = "DRAM: Random traffic; \
DRAM_ROTATE: Traffic rotating across banks and ranks")
-parser.add_option("--addr_map", type="int", default=1,
- help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo")
+parser.add_option("--addr-map", type="choice",
+ choices=ObjectList.dram_addr_map_list.get_names(),
+ default="RoRaBaCoCh", help = "DRAM address map policy")
(options, args) = parser.parse_args()
if args:
- print "Error: script doesn't take any positional arguments"
+ print("Error: script doesn't take any positional arguments")
sys.exit(1)
# at the moment we stay with the default open-adaptive page policy,
options.mem_channels = 1
options.external_memory_system = 0
options.tlm_memory = 0
+options.elastic_trace_en = 0
MemConfig.config_mem(options, system)
# the following assumes that we are using the native DRAM
# controller, check to be sure
-if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
- fatal("This script assumes the memory is a DRAMCtrl subclass")
+if not isinstance(system.mem_ctrls[0], m5.objects.MemCtrl):
+ fatal("This script assumes the controller is a MemCtrl subclass")
+if not isinstance(system.mem_ctrls[0].dram, m5.objects.DRAMInterface):
+ fatal("This script assumes the memory is a DRAMInterface subclass")
# there is no point slowing things down by saving any data
-system.mem_ctrls[0].null = True
+system.mem_ctrls[0].dram.null = True
# Set the address mapping based on input argument
-# Default to RoRaBaCoCh
-if options.addr_map == 0:
- system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh"
-elif options.addr_map == 1:
- system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh"
-else:
- fatal("Did not specify a valid address map argument")
+system.mem_ctrls[0].dram.addr_mapping = options.addr_map
# stay in each state for 0.25 ms, long enough to warm things up, and
# short enough to avoid hitting a refresh
period = 250000000
-# this is where we go off piste, and print the traffic generator
-# configuration that we will later use, crazy but it works
-cfg_file_name = "configs/dram/sweep.cfg"
-cfg_file = open(cfg_file_name, 'w')
-
# stay in each state as long as the dump/reset period, use the entire
# range, issue transactions of the right DRAM burst size, and match
# the DRAM maximum bandwidth to ensure that it is saturated
# get the number of banks
-nbr_banks = system.mem_ctrls[0].banks_per_rank.value
+nbr_banks = system.mem_ctrls[0].dram.banks_per_rank.value
# determine the burst length in bytes
-burst_size = int((system.mem_ctrls[0].devices_per_rank.value *
- system.mem_ctrls[0].device_bus_width.value *
- system.mem_ctrls[0].burst_length.value) / 8)
+burst_size = int((system.mem_ctrls[0].dram.devices_per_rank.value *
+ system.mem_ctrls[0].dram.device_bus_width.value *
+ system.mem_ctrls[0].dram.burst_length.value) / 8)
# next, get the page size in bytes
-page_size = system.mem_ctrls[0].devices_per_rank.value * \
- system.mem_ctrls[0].device_rowbuffer_size.value
+page_size = system.mem_ctrls[0].dram.devices_per_rank.value * \
+ system.mem_ctrls[0].dram.device_rowbuffer_size.value
# match the maximum bandwidth of the memory, the parameter is in seconds
# and we need it in ticks (ps)
-itt = system.mem_ctrls[0].tBURST.value * 1000000000000
+itt = getattr(system.mem_ctrls[0].dram.tBURST_MIN, 'value',
+ system.mem_ctrls[0].dram.tBURST.value) * 1000000000000
# assume we start at 0
max_addr = mem_range.end
# enough
max_stride = min(512, page_size)
-# now we create the state by iterating over the stride size from burst
-# size to the max stride, and from using only a single bank up to the
-# number of banks available
-nxt_state = 0
-for bank in range(1, nbr_banks + 1):
- for stride_size in range(burst_size, max_stride + 1, burst_size):
- cfg_file.write("STATE %d %d %s %d 0 %d %d "
- "%d %d %d %d %d %d %d %d %d\n" %
- (nxt_state, period, options.mode, options.rd_perc,
- max_addr, burst_size, itt, itt, 0, stride_size,
- page_size, nbr_banks, bank, options.addr_map,
- options.mem_ranks))
- nxt_state = nxt_state + 1
-
-cfg_file.write("INIT 0\n")
-
-# go through the states one by one
-for state in range(1, nxt_state):
- cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state))
-
-cfg_file.write("TRANSITION %d %d 1\n" % (nxt_state - 1, nxt_state - 1))
-
-cfg_file.close()
-
# create a traffic generator, and point it to the file we just created
-system.tgen = TrafficGen(config_file = cfg_file_name)
+system.tgen = PyTrafficGen()
# add a communication monitor
system.monitor = CommMonitor()
root.system.mem_mode = 'timing'
m5.instantiate()
-m5.simulate(nxt_state * period)
-print "DRAM sweep with burst: %d, banks: %d, max stride: %d" % \
- (burst_size, nbr_banks, max_stride)
+def trace():
+ addr_map = ObjectList.dram_addr_map_list.get(options.addr_map)
+ generator = dram_generators[options.mode](system.tgen)
+ for stride_size in range(burst_size, max_stride + 1, burst_size):
+ for bank in range(1, nbr_banks + 1):
+ num_seq_pkts = int(math.ceil(float(stride_size) / burst_size))
+ yield generator(period,
+ 0, max_addr, burst_size, int(itt), int(itt),
+ options.rd_perc, 0,
+ num_seq_pkts, page_size, nbr_banks, bank,
+ addr_map, options.mem_ranks)
+ yield system.tgen.createExit(0)
+
+system.tgen.start(trace())
+
+m5.simulate()
+
+print("DRAM sweep with burst: %d, banks: %d, max stride: %d, request \
+ generation period: %d" % (burst_size, nbr_banks, max_stride, itt))
projects / gem5.git / blobdiff