mem: Rename Bus to XBar to better reflect its behaviour

[gem5.git] / configs / example / memtest.py

diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index 5bb874e8543043e7ff0c772389750f687fea668f..eaf3a52bd445227b8e6c2439d4330cb746b79173 100644 (file)
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -26,10 +26,11 @@
 #
 # Authors: Ron Dreslinski
 
+import optparse
+import sys
+
 import m5
 from m5.objects import *
-import os, optparse, sys
-m5.AddToPath('../common')
 
 parser = optparse.OptionParser()
 
@@ -82,6 +83,10 @@ parser.add_option("--progress", type="int", default=1000,
                   metavar="NLOADS",
                   help="Progress message interval "
                   "[default: %default]")
+parser.add_option("--sys-clock", action="store", type="string",
+                  default='1GHz',
+                  help = """Top-level clock for blocks running at system
+                  speed""")
 
 (options, args) = parser.parse_args()
 
@@ -108,13 +113,14 @@ if len(treespec) < 1:
      sys.exit(1)
 
 # define prototype L1 cache
-proto_l1 = BaseCache(size = '32kB', assoc = 4, block_size = block_size,
-                     latency = '1ns', tgts_per_mshr = 8)
+proto_l1 = BaseCache(size = '32kB', assoc = 4,
+                     hit_latency = 1, response_latency = 1,
+                     tgts_per_mshr = 8)
 
 if options.blocking:
      proto_l1.mshrs = 1
 else:
-     proto_l1.mshrs = 8
+     proto_l1.mshrs = 4
 
 # build a list of prototypes, one for each level of treespec, starting
 # at the end (last entry is tester objects)
@@ -128,28 +134,43 @@ if len(treespec) > 1:
      prototypes.insert(0, proto_l1)
 
 # now add additional cache levels (if any) by scaling L1 params
-while len(prototypes) < len(treespec):
+for scale in treespec[:-2]:
      # clone previous level and update params
      prev = prototypes[0]
      next = prev()
-     next.size = prev.size * 4
-     next.latency = prev.latency * 10
-     next.assoc = prev.assoc * 2
+     next.size = prev.size * scale
+     next.hit_latency = prev.hit_latency * 10
+     next.response_latency = prev.response_latency * 10
+     next.assoc = prev.assoc * scale
+     next.mshrs = prev.mshrs * scale
      prototypes.insert(0, next)
 
 # system simulated
-system = System(funcmem = PhysicalMemory(),
-                physmem = PhysicalMemory(latency = "100ns"))
+system = System(funcmem = SimpleMemory(in_addr_map = False),
+                funcbus = NoncoherentXBar(),
+                physmem = SimpleMemory(latency = "100ns"),
+                cache_line_size = block_size)
+
+
+system.voltage_domain = VoltageDomain(voltage = '1V')
+
+system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
+                        voltage_domain = system.voltage_domain)
 
 def make_level(spec, prototypes, attach_obj, attach_port):
      fanout = spec[0]
      parent = attach_obj # use attach obj as config parent too
      if len(spec) > 1 and (fanout > 1 or options.force_bus):
-          new_bus = Bus(clock="500MHz", width=16)
-          new_bus.port = getattr(attach_obj, attach_port)
+          port = getattr(attach_obj, attach_port)
+          new_bus = CoherentXBar(width=16)
+          if (port.role == 'MASTER'):
+               new_bus.slave = port
+               attach_port = "master"
+          else:
+               new_bus.master = port
+               attach_port = "slave"
           parent.cpu_side_bus = new_bus
           attach_obj = new_bus
-          attach_port = "port"
      objs = [prototypes[0]() for i in xrange(fanout)]
      if len(spec) > 1:
           # we just built caches, more levels to go
@@ -162,25 +183,32 @@ def make_level(spec, prototypes, attach_obj, attach_port):
           parent.cpu = objs
           for t in objs:
                t.test = getattr(attach_obj, attach_port)
-               t.functional = system.funcmem.port
+               t.functional = system.funcbus.slave
 
 make_level(treespec, prototypes, system.physmem, "port")
 
+# connect reference memory to funcbus
+system.funcbus.master = system.funcmem.port
+
 # -----------------------
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 if options.atomic:
     root.system.mem_mode = 'atomic'
 else:
     root.system.mem_mode = 'timing'
 
+# The system port is never used in the tester so merely connect it
+# to avoid problems
+root.system.system_port = root.system.funcbus.slave
+
 # Not much point in this being higher than the L1 latency
 m5.ticks.setGlobalFrequency('1ns')
 
 # instantiate configuration
-m5.instantiate(root)
+m5.instantiate()
 
 # simulate until program terminates
 exit_event = m5.simulate(options.maxtick)