mem: Rename Bus to XBar to better reflect its behaviour

[gem5.git] / configs / example / memtest.py

diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index e8dc52fb522add832087cc5213fec9ca7d2329e0..eaf3a52bd445227b8e6c2439d4330cb746b79173 100644 (file)
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -83,6 +83,10 @@ parser.add_option("--progress", type="int", default=1000,
                   metavar="NLOADS",
                   help="Progress message interval "
                   "[default: %default]")
+parser.add_option("--sys-clock", action="store", type="string",
+                  default='1GHz',
+                  help = """Top-level clock for blocks running at system
+                  speed""")
 
 (options, args) = parser.parse_args()
 
@@ -109,8 +113,8 @@ if len(treespec) < 1:
      sys.exit(1)
 
 # define prototype L1 cache
-proto_l1 = BaseCache(size = '32kB', assoc = 4, block_size = block_size,
-                     hit_latency = '1ns', response_latency = '1ns',
+proto_l1 = BaseCache(size = '32kB', assoc = 4,
+                     hit_latency = 1, response_latency = 1,
                      tgts_per_mshr = 8)
 
 if options.blocking:
@@ -135,23 +139,30 @@ for scale in treespec[:-2]:
      prev = prototypes[0]
      next = prev()
      next.size = prev.size * scale
-     next.latency = prev.latency * 10
+     next.hit_latency = prev.hit_latency * 10
+     next.response_latency = prev.response_latency * 10
      next.assoc = prev.assoc * scale
      next.mshrs = prev.mshrs * scale
      prototypes.insert(0, next)
 
 # system simulated
 system = System(funcmem = SimpleMemory(in_addr_map = False),
-                funcbus = NoncoherentBus(),
-                physmem = SimpleMemory(latency = "100ns"))
-system.clock = options.sys_clock
+                funcbus = NoncoherentXBar(),
+                physmem = SimpleMemory(latency = "100ns"),
+                cache_line_size = block_size)
+
+
+system.voltage_domain = VoltageDomain(voltage = '1V')
+
+system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
+                        voltage_domain = system.voltage_domain)
 
 def make_level(spec, prototypes, attach_obj, attach_port):
      fanout = spec[0]
      parent = attach_obj # use attach obj as config parent too
      if len(spec) > 1 and (fanout > 1 or options.force_bus):
           port = getattr(attach_obj, attach_port)
-          new_bus = CoherentBus(clock="500MHz", width=16)
+          new_bus = CoherentXBar(width=16)
           if (port.role == 'MASTER'):
                new_bus.slave = port
                attach_port = "master"