CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable

[gem5.git] / configs / example / se.py

diff --git a/configs/example/se.py b/configs/example/se.py
index 35025a8ff27a292780610522ab5f6a3fc96a6740..09e3d69faffe4ed69e47af31ca43139fe838399c 100644 (file)
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -82,10 +82,8 @@ parser.add_option("--errout", default="", help="Redirect stderr to a file.")
 
 execfile(os.path.join(config_root, "common", "Options.py"))
 
-if buildEnv['PROTOCOL'] != 'None':
-    parser.add_option("--ruby", action="store_true")
-    if '--ruby' in sys.argv:
-        Ruby.define_options(parser)
+if '--ruby' in sys.argv:
+    Ruby.define_options(parser)
 
 (options, args) = parser.parse_args()
 
@@ -177,25 +175,28 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
                 physmem = PhysicalMemory(range=AddrRange("512MB")),
                 membus = Bus(), mem_mode = test_mem_mode)
 
-if options.ruby:
-    options.use_map = True
-    Ruby.create_system(options, system)
-    assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
-else:
-    system.system_port = system.membus.port
-    system.physmem.port = system.membus.port
-    CacheConfig.config_cache(options, system)
-
 for i in xrange(np):
     system.cpu[i].workload = multiprocesses[i]
 
     if options.ruby:
-        system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port
-        system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port
+        system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].slave
+        system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].slave
 
     if options.fastmem:
         system.cpu[0].physmem_port = system.physmem.port
 
+    if options.checker:
+        system.cpu[i].addCheckerCpu()
+
+if options.ruby:
+    options.use_map = True
+    Ruby.create_system(options, system)
+    assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+else:
+    system.system_port = system.membus.slave
+    system.physmem.port = system.membus.master
+    CacheConfig.config_cache(options, system)
+
 root = Root(full_system = False, system = system)
 
 Simulation.run(options, root, system, FutureClass)