-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt
# Simple test script
#
# "m5 test.py"
+from __future__ import print_function
+from __future__ import absolute_import
+
import optparse
import sys
+import os
import m5
from m5.defines import buildEnv
from m5.objects import *
-from m5.util import addToPath, fatal
+from m5.params import NULL
+from m5.util import addToPath, fatal, warn
+
+addToPath('../')
+
+from ruby import Ruby
-addToPath('../common')
-addToPath('../ruby')
+from common import Options
+from common import Simulation
+from common import CacheConfig
+from common import CpuConfig
+from common import ObjectList
+from common import MemConfig
+from common.FileSystemConfig import config_filesystem
+from common.Caches import *
+from common.cpu2000 import *
+
+def get_processes(options):
+ """Interprets provided options and returns a list of processes"""
+
+ multiprocesses = []
+ inputs = []
+ outputs = []
+ errouts = []
+ pargs = []
+
+ workloads = options.cmd.split(';')
+ if options.input != "":
+ inputs = options.input.split(';')
+ if options.output != "":
+ outputs = options.output.split(';')
+ if options.errout != "":
+ errouts = options.errout.split(';')
+ if options.options != "":
+ pargs = options.options.split(';')
+
+ idx = 0
+ for wrkld in workloads:
+ process = Process(pid = 100 + idx)
+ process.executable = wrkld
+ process.cwd = os.getcwd()
+
+ if options.env:
+ with open(options.env, 'r') as f:
+ process.env = [line.rstrip() for line in f]
+
+ if len(pargs) > idx:
+ process.cmd = [wrkld] + pargs[idx].split()
+ else:
+ process.cmd = [wrkld]
+
+ if len(inputs) > idx:
+ process.input = inputs[idx]
+ if len(outputs) > idx:
+ process.output = outputs[idx]
+ if len(errouts) > idx:
+ process.errout = errouts[idx]
+
+ multiprocesses.append(process)
+ idx += 1
+
+ if options.smt:
+ assert(options.cpu_type == "DerivO3CPU")
+ return multiprocesses, idx
+ else:
+ return multiprocesses, 1
-import Options
-import Ruby
-import Simulation
-import CacheConfig
-from Caches import *
-from cpu2000 import *
parser = optparse.OptionParser()
Options.addCommonOptions(parser)
(options, args) = parser.parse_args()
if args:
- print "Error: script doesn't take any positional arguments"
+ print("Error: script doesn't take any positional arguments")
sys.exit(1)
multiprocesses = []
-apps = []
+numThreads = 1
if options.bench:
apps = options.bench.split("-")
if len(apps) != options.num_cpus:
- print "number of benchmarks not equal to set num_cpus!"
+ print("number of benchmarks not equal to set num_cpus!")
sys.exit(1)
for app in apps:
try:
- if buildEnv['TARGET_ISA'] == 'alpha':
- exec("workload = %s('alpha', 'tru64', 'ref')" % app)
+ if buildEnv['TARGET_ISA'] == 'arm':
+ exec("workload = %s('arm_%s', 'linux', '%s')" % (
+ app, options.arm_iset, options.spec_input))
else:
- exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app)
- multiprocesses.append(workload.makeLiveProcess())
+ exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
+ app, options.spec_input))
+ multiprocesses.append(workload.makeProcess())
except:
- print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
+ print("Unable to find workload for %s: %s" %
+ (buildEnv['TARGET_ISA'], app),
+ file=sys.stderr)
sys.exit(1)
elif options.cmd:
- process = LiveProcess()
- process.executable = options.cmd
- process.cmd = [options.cmd] + options.options.split()
- multiprocesses.append(process)
+ multiprocesses, numThreads = get_processes(options)
else:
- print >> sys.stderr, "No workload specified. Exiting!\n"
+ print("No workload specified. Exiting!\n", file=sys.stderr)
sys.exit(1)
-if options.input != "":
- process.input = options.input
-if options.output != "":
- process.output = options.output
-if options.errout != "":
- process.errout = options.errout
-
-
-# By default, set workload to path of user-specified binary
-workloads = options.cmd
-numThreads = 1
-
-if options.cpu_type == "detailed" or options.cpu_type == "inorder":
- #check for SMT workload
- workloads = options.cmd.split(';')
- if len(workloads) > 1:
- process = []
- smt_idx = 0
- inputs = []
- outputs = []
- errouts = []
-
- if options.input != "":
- inputs = options.input.split(';')
- if options.output != "":
- outputs = options.output.split(';')
- if options.errout != "":
- errouts = options.errout.split(';')
-
- for wrkld in workloads:
- smt_process = LiveProcess()
- smt_process.executable = wrkld
- smt_process.cmd = wrkld + " " + options.options
- if inputs and inputs[smt_idx]:
- smt_process.input = inputs[smt_idx]
- if outputs and outputs[smt_idx]:
- smt_process.output = outputs[smt_idx]
- if errouts and errouts[smt_idx]:
- smt_process.errout = errouts[smt_idx]
- process += [smt_process, ]
- smt_idx += 1
- numThreads = len(workloads)
-
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
-CPUClass.clock = '2GHz'
-CPUClass.numThreads = numThreads;
+CPUClass.numThreads = numThreads
-np = options.num_cpus
+# Check -- do not allow SMT with multiple CPUs
+if options.smt and options.num_cpus > 1:
+ fatal("You cannot use SMT with multiple CPUs!")
-system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
- physmem = SimpleMemory(range=AddrRange("512MB")),
- membus = CoherentBus(), mem_mode = test_mem_mode)
+np = options.num_cpus
+system = System(cpu = [CPUClass(cpu_id=i) for i in range(np)],
+ mem_mode = test_mem_mode,
+ mem_ranges = [AddrRange(options.mem_size)],
+ cache_line_size = options.cacheline_size,
+ workload = NULL)
+
+if numThreads > 1:
+ system.multi_thread = True
+
+# Create a top-level voltage domain
+system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+
+# Create a source clock for the system and set the clock period
+system.clk_domain = SrcClockDomain(clock = options.sys_clock,
+ voltage_domain = system.voltage_domain)
+
+# Create a CPU voltage domain
+system.cpu_voltage_domain = VoltageDomain()
+
+# Create a separate clock domain for the CPUs
+system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
+ voltage_domain =
+ system.cpu_voltage_domain)
+
+# If elastic tracing is enabled, then configure the cpu and attach the elastic
+# trace probe
+if options.elastic_trace_en:
+ CpuConfig.config_etrace(CPUClass, system.cpu, options)
+
+# All cpus belong to a common cpu_clk_domain, therefore running at a common
+# frequency.
+for cpu in system.cpu:
+ cpu.clk_domain = system.cpu_clk_domain
+
+if ObjectList.is_kvm_cpu(CPUClass) or ObjectList.is_kvm_cpu(FutureClass):
+ if buildEnv['TARGET_ISA'] == 'x86':
+ system.kvm_vm = KvmVM()
+ for process in multiprocesses:
+ process.useArchPT = True
+ process.kvmInSE = True
+ else:
+ fatal("KvmCPU can only be used in SE mode with x86")
# Sanity check
-if options.fastmem and (options.caches or options.l2cache):
- fatal("You cannot use fastmem in combination with caches!")
-
-for i in xrange(np):
- if len(multiprocesses) == 1:
+if options.simpoint_profile:
+ if not ObjectList.is_noncaching_cpu(CPUClass):
+ fatal("SimPoint/BPProbe should be done with an atomic cpu")
+ if np > 1:
+ fatal("SimPoint generation not supported with more than one CPUs")
+
+for i in range(np):
+ if options.smt:
+ system.cpu[i].workload = multiprocesses
+ elif len(multiprocesses) == 1:
system.cpu[i].workload = multiprocesses[0]
else:
system.cpu[i].workload = multiprocesses[i]
- if options.fastmem:
- system.cpu[i].fastmem = True
+ if options.simpoint_profile:
+ system.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
system.cpu[i].addCheckerCpu()
-if options.ruby:
- if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
- print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
- sys.exit(1)
+ if options.bp_type:
+ bpClass = ObjectList.bp_list.get(options.bp_type)
+ system.cpu[i].branchPred = bpClass()
- options.use_map = True
- Ruby.create_system(options, system)
- assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+ if options.indirect_bp_type:
+ indirectBPClass = \
+ ObjectList.indirect_bp_list.get(options.indirect_bp_type)
+ system.cpu[i].branchPred.indirectBranchPred = indirectBPClass()
+
+ system.cpu[i].createThreads()
+
+if options.ruby:
+ Ruby.create_system(options, False, system)
+ assert(options.num_cpus == len(system.ruby._cpu_ports))
- for i in xrange(np):
- ruby_port = system.ruby._cpu_ruby_ports[i]
+ system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+ voltage_domain = system.voltage_domain)
+ for i in range(np):
+ ruby_port = system.ruby._cpu_ports[i]
# Create the interrupt controller and connect its ports to Ruby
+ # Note that the interrupt controller is always present but only
+ # in x86 does it have message ports that need to be connected
system.cpu[i].createInterruptController()
- system.cpu[i].interrupts.pio = ruby_port.master
- system.cpu[i].interrupts.int_master = ruby_port.slave
- system.cpu[i].interrupts.int_slave = ruby_port.master
# Connect the cpu's cache ports to Ruby
system.cpu[i].icache_port = ruby_port.slave
system.cpu[i].dcache_port = ruby_port.slave
+ if buildEnv['TARGET_ISA'] == 'x86':
+ system.cpu[i].interrupts[0].pio = ruby_port.master
+ system.cpu[i].interrupts[0].int_master = ruby_port.slave
+ system.cpu[i].interrupts[0].int_slave = ruby_port.master
+ system.cpu[i].itb.walker.port = ruby_port.slave
+ system.cpu[i].dtb.walker.port = ruby_port.slave
else:
+ MemClass = Simulation.setMemClass(options)
+ system.membus = SystemXBar()
system.system_port = system.membus.slave
- system.physmem.port = system.membus.master
CacheConfig.config_cache(options, system)
+ MemConfig.config_mem(options, system)
+ config_filesystem(system, options)
root = Root(full_system = False, system = system)
Simulation.run(options, root, system, FutureClass)
projects / gem5.git / blobdiff