# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt
# Simple test script
#
# "m5 test.py"
+from __future__ import print_function
+from __future__ import absolute_import
+
import optparse
import sys
import os
import m5
from m5.defines import buildEnv
from m5.objects import *
-from m5.util import addToPath, fatal
+from m5.params import NULL
+from m5.util import addToPath, fatal, warn
-addToPath('../common')
-addToPath('../ruby')
+addToPath('../')
-import Options
-import Ruby
-import Simulation
-import CacheConfig
-import MemConfig
-from Caches import *
-from cpu2000 import *
+from ruby import Ruby
+
+from common import Options
+from common import Simulation
+from common import CacheConfig
+from common import CpuConfig
+from common import ObjectList
+from common import MemConfig
+from common.FileSystemConfig import config_filesystem
+from common.Caches import *
+from common.cpu2000 import *
def get_processes(options):
"""Interprets provided options and returns a list of processes"""
idx = 0
for wrkld in workloads:
- process = LiveProcess()
+ process = Process(pid = 100 + idx)
process.executable = wrkld
process.cwd = os.getcwd()
+ if options.env:
+ with open(options.env, 'r') as f:
+ process.env = [line.rstrip() for line in f]
+
if len(pargs) > idx:
process.cmd = [wrkld] + pargs[idx].split()
else:
idx += 1
if options.smt:
- assert(options.cpu_type == "detailed" or options.cpu_type == "inorder")
+ assert(options.cpu_type == "DerivO3CPU")
return multiprocesses, idx
else:
return multiprocesses, 1
(options, args) = parser.parse_args()
if args:
- print "Error: script doesn't take any positional arguments"
+ print("Error: script doesn't take any positional arguments")
sys.exit(1)
multiprocesses = []
if options.bench:
apps = options.bench.split("-")
if len(apps) != options.num_cpus:
- print "number of benchmarks not equal to set num_cpus!"
+ print("number of benchmarks not equal to set num_cpus!")
sys.exit(1)
for app in apps:
try:
- if buildEnv['TARGET_ISA'] == 'alpha':
- exec("workload = %s('alpha', 'tru64', '%s')" % (
- app, options.spec_input))
- elif buildEnv['TARGET_ISA'] == 'arm':
+ if buildEnv['TARGET_ISA'] == 'arm':
exec("workload = %s('arm_%s', 'linux', '%s')" % (
app, options.arm_iset, options.spec_input))
else:
exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
app, options.spec_input))
- multiprocesses.append(workload.makeLiveProcess())
+ multiprocesses.append(workload.makeProcess())
except:
- print >>sys.stderr, "Unable to find workload for %s: %s" % (
- buildEnv['TARGET_ISA'], app)
+ print("Unable to find workload for %s: %s" %
+ (buildEnv['TARGET_ISA'], app),
+ file=sys.stderr)
sys.exit(1)
elif options.cmd:
multiprocesses, numThreads = get_processes(options)
else:
- print >> sys.stderr, "No workload specified. Exiting!\n"
+ print("No workload specified. Exiting!\n", file=sys.stderr)
sys.exit(1)
fatal("You cannot use SMT with multiple CPUs!")
np = options.num_cpus
-system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
+system = System(cpu = [CPUClass(cpu_id=i) for i in range(np)],
mem_mode = test_mem_mode,
mem_ranges = [AddrRange(options.mem_size)],
- cache_line_size = options.cacheline_size)
+ cache_line_size = options.cacheline_size,
+ workload = NULL)
+
+if numThreads > 1:
+ system.multi_thread = True
# Create a top-level voltage domain
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
voltage_domain =
system.cpu_voltage_domain)
+# If elastic tracing is enabled, then configure the cpu and attach the elastic
+# trace probe
+if options.elastic_trace_en:
+ CpuConfig.config_etrace(CPUClass, system.cpu, options)
+
# All cpus belong to a common cpu_clk_domain, therefore running at a common
# frequency.
for cpu in system.cpu:
cpu.clk_domain = system.cpu_clk_domain
-# Sanity check
-if options.fastmem:
- if CPUClass != AtomicSimpleCPU:
- fatal("Fastmem can only be used with atomic CPU!")
- if (options.caches or options.l2cache):
- fatal("You cannot use fastmem in combination with caches!")
+if ObjectList.is_kvm_cpu(CPUClass) or ObjectList.is_kvm_cpu(FutureClass):
+ if buildEnv['TARGET_ISA'] == 'x86':
+ system.kvm_vm = KvmVM()
+ for process in multiprocesses:
+ process.useArchPT = True
+ process.kvmInSE = True
+ else:
+ fatal("KvmCPU can only be used in SE mode with x86")
+# Sanity check
if options.simpoint_profile:
- if not options.fastmem:
- # Atomic CPU checked with fastmem option already
- fatal("SimPoint generation should be done with atomic cpu and fastmem")
+ if not ObjectList.is_noncaching_cpu(CPUClass):
+ fatal("SimPoint/BPProbe should be done with an atomic cpu")
if np > 1:
fatal("SimPoint generation not supported with more than one CPUs")
-for i in xrange(np):
+for i in range(np):
if options.smt:
system.cpu[i].workload = multiprocesses
elif len(multiprocesses) == 1:
else:
system.cpu[i].workload = multiprocesses[i]
- if options.fastmem:
- system.cpu[i].fastmem = True
-
if options.simpoint_profile:
- system.cpu[i].simpoint_profile = True
- system.cpu[i].simpoint_interval = options.simpoint_interval
+ system.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
system.cpu[i].addCheckerCpu()
+ if options.bp_type:
+ bpClass = ObjectList.bp_list.get(options.bp_type)
+ system.cpu[i].branchPred = bpClass()
+
+ if options.indirect_bp_type:
+ indirectBPClass = \
+ ObjectList.indirect_bp_list.get(options.indirect_bp_type)
+ system.cpu[i].branchPred.indirectBranchPred = indirectBPClass()
+
system.cpu[i].createThreads()
if options.ruby:
- if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
- print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
- sys.exit(1)
-
- # Use SimpleMemory with the null option since this memory is only used
- # for determining which addresses are within the range of the memory.
- # No space allocation is required.
- system.physmem = SimpleMemory(range=AddrRange(options.mem_size),
- null = True)
- options.use_map = True
- Ruby.create_system(options, system)
+ Ruby.create_system(options, False, system)
assert(options.num_cpus == len(system.ruby._cpu_ports))
- for i in xrange(np):
+ system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+ voltage_domain = system.voltage_domain)
+ for i in range(np):
ruby_port = system.ruby._cpu_ports[i]
# Create the interrupt controller and connect its ports to Ruby
system.cpu[i].icache_port = ruby_port.slave
system.cpu[i].dcache_port = ruby_port.slave
if buildEnv['TARGET_ISA'] == 'x86':
- system.cpu[i].interrupts.pio = ruby_port.master
- system.cpu[i].interrupts.int_master = ruby_port.slave
- system.cpu[i].interrupts.int_slave = ruby_port.master
+ system.cpu[i].interrupts[0].pio = ruby_port.master
+ system.cpu[i].interrupts[0].int_master = ruby_port.slave
+ system.cpu[i].interrupts[0].int_slave = ruby_port.master
system.cpu[i].itb.walker.port = ruby_port.slave
system.cpu[i].dtb.walker.port = ruby_port.slave
else:
MemClass = Simulation.setMemClass(options)
- system.membus = CoherentBus()
+ system.membus = SystemXBar()
system.system_port = system.membus.slave
CacheConfig.config_cache(options, system)
MemConfig.config_mem(options, system)
+ config_filesystem(system, options)
root = Root(full_system = False, system = system)
Simulation.run(options, root, system, FutureClass)
projects / gem5.git / blobdiff