Add --force-bus option to memtest.py.

[gem5.git] / configs / example / se.py

diff --git a/configs/example/se.py b/configs/example/se.py
index 46f2d4a1aa195fbf2cf887d6fb11d136c114ad7f..b294480f64d4bd9f6e5e697414a82c1b949038b8 100644 (file)
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -88,16 +88,7 @@ if options.detailed:
             process += [smt_process, ]
             smt_idx += 1
 
-
-if options.timing:
-    CPUClass = TimingSimpleCPU
-    test_mem_mode = 'timing'
-elif options.detailed:
-    CPUClass = DerivO3CPU
-    test_mem_mode = 'timing'
-else:
-    CPUClass = AtomicSimpleCPU
-    test_mem_mode = 'atomic'
+(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
 
 CPUClass.clock = '2GHz'
 
@@ -110,12 +101,19 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
 system.physmem.port = system.membus.port
 
 for i in xrange(np):
-    if options.caches and not options.standard_switch:
+    if options.caches:
         system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
                                               L1Cache(size = '64kB'))
-    system.cpu[i].connectMemPorts(system.membus)
+    if options.l2cache:
+        system.l2 = L2Cache(size='2MB')
+        system.tol2bus = Bus()
+        system.l2.cpu_side = system.tol2bus.port
+        system.l2.mem_side = system.membus.port
+        system.cpu[i].connectMemPorts(system.tol2bus)
+    else:
+        system.cpu[i].connectMemPorts(system.membus)
     system.cpu[i].workload = process
 
 root = Root(system = system)
 
-Simulation.run(options, root, system)
+Simulation.run(options, root, system, FutureClass)