Add --force-bus option to memtest.py.

[gem5.git] / configs / example / se.py

diff --git a/configs/example/se.py b/configs/example/se.py
index d1d19eebc5fc0b1068011ebe25a32b908d698a90..b294480f64d4bd9f6e5e697414a82c1b949038b8 100644 (file)
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -34,21 +34,27 @@ import m5
 from m5.objects import *
 import os, optparse, sys
 m5.AddToPath('../common')
-from FullO3Config import *
+import Simulation
+from Caches import *
+
+# Get paths we might need.  It's expected this file is in m5/configs/example.
+config_path = os.path.dirname(os.path.abspath(__file__))
+config_root = os.path.dirname(config_path)
+m5_root = os.path.dirname(config_root)
 
 parser = optparse.OptionParser()
 
+# Benchmark options
 parser.add_option("-c", "--cmd",
-                  default="../../tests/test-progs/hello/bin/alpha/linux/hello",
+                  default=os.path.join(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"),
                   help="The binary to run in syscall emulation mode.")
 parser.add_option("-o", "--options", default="",
                   help="The options to pass to the binary, use \" \" around the entire\
                         string.")
 parser.add_option("-i", "--input", default="",
                   help="A file of input to give to the binary.")
-parser.add_option("-d", "--detailed", action="store_true")
-parser.add_option("-t", "--timing", action="store_true")
-parser.add_option("-m", "--maxtick", type="int")
+
+execfile(os.path.join(config_root, "common", "Options.py"))
 
 (options, args) = parser.parse_args()
 
@@ -82,37 +88,32 @@ if options.detailed:
             process += [smt_process, ]
             smt_idx += 1
 
+(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
 
-if options.timing:
-    cpu = TimingSimpleCPU()
-elif options.detailed:
-    cpu = DetailedO3CPU()
-else:
-    cpu = AtomicSimpleCPU()
-
-cpu.workload = process
-cpu.cpu_id = 0
-
-system = System(cpu = cpu,
-                physmem = PhysicalMemory(),
-                membus = Bus())
-system.physmem.port = system.membus.port
-system.cpu.connectMemPorts(system.membus)
-system.cpu.mem = system.physmem
+CPUClass.clock = '2GHz'
 
-root = Root(system = system)
+np = options.num_cpus
 
-if options.timing or options.detailed:
-    root.system.mem_mode = 'timing'
+system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
+                physmem = PhysicalMemory(range=AddrRange("512MB")),
+                membus = Bus(), mem_mode = test_mem_mode)
 
-# instantiate configuration
-m5.instantiate(root)
+system.physmem.port = system.membus.port
 
-# simulate until program terminates
-if options.maxtick:
-    exit_event = m5.simulate(options.maxtick)
-else:
-    exit_event = m5.simulate()
+for i in xrange(np):
+    if options.caches:
+        system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
+                                              L1Cache(size = '64kB'))
+    if options.l2cache:
+        system.l2 = L2Cache(size='2MB')
+        system.tol2bus = Bus()
+        system.l2.cpu_side = system.tol2bus.port
+        system.l2.mem_side = system.membus.port
+        system.cpu[i].connectMemPorts(system.tol2bus)
+    else:
+        system.cpu[i].connectMemPorts(system.membus)
+    system.cpu[i].workload = process
 
-print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
+root = Root(system = system)
 
+Simulation.run(options, root, system, FutureClass)