+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2006-2008 The Regents of The University of Michigan
# All rights reserved.
#
#
# "m5 test.py"
+import optparse
+import sys
+
import m5
+from m5.defines import buildEnv
+from m5.objects import *
+from m5.util import addToPath, fatal
-if m5.build_env['FULL_SYSTEM']:
- m5.fatal("This script requires syscall emulation mode (*_SE).")
+addToPath('../common')
+addToPath('../ruby')
+addToPath('../topologies')
-from m5.objects import *
-import os, optparse, sys
-from os.path import join as joinpath
-m5.AddToPath('../common')
+import Options
+import Ruby
import Simulation
+import CacheConfig
from Caches import *
from cpu2000 import *
-# Get paths we might need. It's expected this file is in m5/configs/example.
-config_path = os.path.dirname(os.path.abspath(__file__))
-config_root = os.path.dirname(config_path)
-m5_root = os.path.dirname(config_root)
-
parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
+Options.addSEOptions(parser)
-# Benchmark options
-parser.add_option("-c", "--cmd",
- default=joinpath(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"),
- help="The binary to run in syscall emulation mode.")
-parser.add_option("-o", "--options", default="",
- help='The options to pass to the binary, use " " around the entire string')
-parser.add_option("-i", "--input", default="", help="Read stdin from a file.")
-parser.add_option("--output", default="", help="Redirect stdout to a file.")
-parser.add_option("--errout", default="", help="Redirect stderr to a file.")
-
-execfile(os.path.join(config_root, "common", "Options.py"))
+if '--ruby' in sys.argv:
+ Ruby.define_options(parser)
(options, args) = parser.parse_args()
print "Error: script doesn't take any positional arguments"
sys.exit(1)
+multiprocesses = []
+apps = []
+
if options.bench:
- try:
- if m5.build_env['TARGET_ISA'] != 'alpha':
- print >>sys.stderr, "Simpoints code only works for Alpha ISA at this time"
- sys.exit(1)
- exec("workload = %s('alpha', 'tru64', 'ref')" % options.bench)
- process = workload.makeLiveProcess()
- except:
- print >>sys.stderr, "Unable to find workload for %s" % options.bench
+ apps = options.bench.split("-")
+ if len(apps) != options.num_cpus:
+ print "number of benchmarks not equal to set num_cpus!"
sys.exit(1)
-else:
+
+ for app in apps:
+ try:
+ if buildEnv['TARGET_ISA'] == 'alpha':
+ exec("workload = %s('alpha', 'tru64', 'ref')" % app)
+ else:
+ exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app)
+ multiprocesses.append(workload.makeLiveProcess())
+ except:
+ print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
+ sys.exit(1)
+elif options.cmd:
process = LiveProcess()
process.executable = options.cmd
process.cmd = [options.cmd] + options.options.split()
+ multiprocesses.append(process)
+else:
+ print >> sys.stderr, "No workload specified. Exiting!\n"
+ sys.exit(1)
if options.input != "":
# By default, set workload to path of user-specified binary
workloads = options.cmd
+numThreads = 1
-if options.detailed:
+if options.cpu_type == "detailed" or options.cpu_type == "inorder":
#check for SMT workload
workloads = options.cmd.split(';')
if len(workloads) > 1:
smt_process.errout = errouts[smt_idx]
process += [smt_process, ]
smt_idx += 1
+ numThreads = len(workloads)
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
-
CPUClass.clock = '2GHz'
-CPUClass.numThreads = len(workloads)
+CPUClass.numThreads = numThreads;
np = options.num_cpus
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
- physmem = PhysicalMemory(range=AddrRange("512MB")),
- membus = Bus(), mem_mode = test_mem_mode)
-
-system.physmem.port = system.membus.port
+ physmem = SimpleMemory(range=AddrRange("512MB")),
+ membus = CoherentBus(), mem_mode = test_mem_mode)
-if options.l2cache:
- system.l2 = L2Cache(size='2MB')
- system.tol2bus = Bus()
- system.l2.cpu_side = system.tol2bus.port
- system.l2.mem_side = system.membus.port
+# Sanity check
+if options.fastmem and (options.caches or options.l2cache):
+ fatal("You cannot use fastmem in combination with caches!")
for i in xrange(np):
- if options.caches:
- system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
- L1Cache(size = '64kB'))
- if options.l2cache:
- system.cpu[i].connectMemPorts(system.tol2bus)
+ if len(multiprocesses) == 1:
+ system.cpu[i].workload = multiprocesses[0]
else:
- system.cpu[i].connectMemPorts(system.membus)
- system.cpu[i].workload = process
+ system.cpu[i].workload = multiprocesses[i]
if options.fastmem:
- system.cpu[0].physmem_port = system.physmem.port
+ system.cpu[i].fastmem = True
+
+ if options.checker:
+ system.cpu[i].addCheckerCpu()
-root = Root(system = system)
+if options.ruby:
+ if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
+ print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
+ sys.exit(1)
+
+ options.use_map = True
+ Ruby.create_system(options, system)
+ assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+
+ for i in xrange(np):
+ ruby_port = system.ruby._cpu_ruby_ports[i]
+
+ # Create the interrupt controller and connect its ports to Ruby
+ system.cpu[i].createInterruptController()
+ system.cpu[i].interrupts.pio = ruby_port.master
+ system.cpu[i].interrupts.int_master = ruby_port.slave
+ system.cpu[i].interrupts.int_slave = ruby_port.master
+
+ # Connect the cpu's cache ports to Ruby
+ system.cpu[i].icache_port = ruby_port.slave
+ system.cpu[i].dcache_port = ruby_port.slave
+else:
+ system.system_port = system.membus.slave
+ system.physmem.port = system.membus.master
+ CacheConfig.config_cache(options, system)
+root = Root(full_system = False, system = system)
Simulation.run(options, root, system, FutureClass)
projects / gem5.git / blobdiff