-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2006-2008 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
#
# "m5 test.py"
+import optparse
+import sys
+
import m5
+from m5.defines import buildEnv
from m5.objects import *
-import os, optparse, sys
-m5.AddToPath('../common')
+from m5.util import addToPath, fatal
+
+addToPath('../common')
+addToPath('../ruby')
+addToPath('../topologies')
+
+import Options
+import Ruby
+import Simulation
+import CacheConfig
+from Caches import *
+from cpu2000 import *
parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
+Options.addSEOptions(parser)
-parser.add_option("-c", "--cmd",
- default="../../tests/test-progs/hello/bin/alpha/linux/hello",
- help="The binary to run in syscall emulation mode.")
-parser.add_option("-o", "--options", default="",
- help="The options to pass to the binary, use \" \" around the entire\
- string.")
-parser.add_option("-i", "--input", default="",
- help="A file of input to give to the binary.")
-parser.add_option("-d", "--detailed", action="store_true")
-parser.add_option("-t", "--timing", action="store_true")
-parser.add_option("-m", "--maxtick", type="int")
+if '--ruby' in sys.argv:
+ Ruby.define_options(parser)
(options, args) = parser.parse_args()
print "Error: script doesn't take any positional arguments"
sys.exit(1)
-process = LiveProcess()
-process.executable = options.cmd
-process.cmd = options.cmd + " " + options.options
+multiprocesses = []
+apps = []
+
+if options.bench:
+ apps = options.bench.split("-")
+ if len(apps) != options.num_cpus:
+ print "number of benchmarks not equal to set num_cpus!"
+ sys.exit(1)
+
+ for app in apps:
+ try:
+ if buildEnv['TARGET_ISA'] == 'alpha':
+ exec("workload = %s('alpha', 'tru64', 'ref')" % app)
+ else:
+ exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app)
+ multiprocesses.append(workload.makeLiveProcess())
+ except:
+ print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
+ sys.exit(1)
+elif options.cmd:
+ process = LiveProcess()
+ process.executable = options.cmd
+ process.cmd = [options.cmd] + options.options.split()
+ multiprocesses.append(process)
+else:
+ print >> sys.stderr, "No workload specified. Exiting!\n"
+ sys.exit(1)
+
+
if options.input != "":
process.input = options.input
+if options.output != "":
+ process.output = options.output
+if options.errout != "":
+ process.errout = options.errout
+
+
+# By default, set workload to path of user-specified binary
+workloads = options.cmd
+numThreads = 1
-if options.detailed:
+if options.cpu_type == "detailed" or options.cpu_type == "inorder":
#check for SMT workload
workloads = options.cmd.split(';')
if len(workloads) > 1:
process = []
smt_idx = 0
inputs = []
+ outputs = []
+ errouts = []
if options.input != "":
inputs = options.input.split(';')
+ if options.output != "":
+ outputs = options.output.split(';')
+ if options.errout != "":
+ errouts = options.errout.split(';')
for wrkld in workloads:
smt_process = LiveProcess()
smt_process.cmd = wrkld + " " + options.options
if inputs and inputs[smt_idx]:
smt_process.input = inputs[smt_idx]
+ if outputs and outputs[smt_idx]:
+ smt_process.output = outputs[smt_idx]
+ if errouts and errouts[smt_idx]:
+ smt_process.errout = errouts[smt_idx]
process += [smt_process, ]
smt_idx += 1
+ numThreads = len(workloads)
+(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
+CPUClass.clock = '2GHz'
+CPUClass.numThreads = numThreads;
-if options.timing:
- cpu = TimingSimpleCPU()
-elif options.detailed:
- cpu = DerivO3CPU()
-else:
- cpu = AtomicSimpleCPU()
+np = options.num_cpus
-cpu.workload = process
-cpu.cpu_id = 0
+system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
+ physmem = SimpleMemory(range=AddrRange("512MB")),
+ membus = CoherentBus(), mem_mode = test_mem_mode)
-system = System(cpu = cpu,
- physmem = PhysicalMemory(),
- membus = Bus())
-system.physmem.port = system.membus.port
-system.cpu.connectMemPorts(system.membus)
-system.cpu.mem = system.physmem
+# Sanity check
+if options.fastmem and (options.caches or options.l2cache):
+ fatal("You cannot use fastmem in combination with caches!")
-root = Root(system = system)
+for i in xrange(np):
+ if len(multiprocesses) == 1:
+ system.cpu[i].workload = multiprocesses[0]
+ else:
+ system.cpu[i].workload = multiprocesses[i]
-if options.timing or options.detailed:
- root.system.mem_mode = 'timing'
+ if options.fastmem:
+ system.cpu[i].fastmem = True
-# instantiate configuration
-m5.instantiate(root)
+ if options.checker:
+ system.cpu[i].addCheckerCpu()
-# simulate until program terminates
-if options.maxtick:
- exit_event = m5.simulate(options.maxtick)
-else:
- exit_event = m5.simulate()
+if options.ruby:
+ if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
+ print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
+ sys.exit(1)
-print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
+ options.use_map = True
+ Ruby.create_system(options, system)
+ assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+
+ for i in xrange(np):
+ ruby_port = system.ruby._cpu_ruby_ports[i]
+
+ # Create the interrupt controller and connect its ports to Ruby
+ system.cpu[i].createInterruptController()
+ system.cpu[i].interrupts.pio = ruby_port.master
+ system.cpu[i].interrupts.int_master = ruby_port.slave
+ system.cpu[i].interrupts.int_slave = ruby_port.master
+
+ # Connect the cpu's cache ports to Ruby
+ system.cpu[i].icache_port = ruby_port.slave
+ system.cpu[i].dcache_port = ruby_port.slave
+else:
+ system.system_port = system.membus.slave
+ system.physmem.port = system.membus.master
+ CacheConfig.config_cache(options, system)
+root = Root(full_system = False, system = system)
+Simulation.run(options, root, system, FutureClass)
projects / gem5.git / blobdiff