configs: ruby: pass the option use_map to directory controller

[gem5.git] / configs / ruby / MESI_CMP_directory.py

diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py
index 6671c307bfe6ca9431e681545c262ca4155a1977..b116371145b1ff70497d32cd12f68e89eeb3422e 100644 (file)
--- a/configs/ruby/MESI_CMP_directory.py
+++ b/configs/ruby/MESI_CMP_directory.py
@@ -31,6 +31,7 @@ import math
 import m5
 from m5.objects import *
 from m5.defines import buildEnv
+from Ruby import create_topology
 
 #
 # Note: the L1 Cache latency is only used by the sequencer on fast path hits
@@ -47,7 +48,7 @@ class L2Cache(RubyCache):
 def define_options(parser):
     return
 
-def create_system(options, system, piobus, dma_devices, ruby_system):
+def create_system(options, system, piobus, dma_ports, ruby_system):
     
     if buildEnv['PROTOCOL'] != 'MESI_CMP_directory':
         panic("This script requires the MESI_CMP_directory protocol to be built.")
@@ -79,10 +80,14 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         #
         l1i_cache = L1Cache(size = options.l1i_size,
                             assoc = options.l1i_assoc,
-                            start_index_bit = block_size_bits)
+                            start_index_bit = block_size_bits,
+                            is_icache = True)
         l1d_cache = L1Cache(size = options.l1d_size,
                             assoc = options.l1d_assoc,
-                            start_index_bit = block_size_bits)
+                            start_index_bit = block_size_bits,
+                            is_icache = False)
+
+        prefetcher = RubyPrefetcher.Prefetcher()
 
         l1_cntrl = L1Cache_Controller(version = i,
                                       cntrl_id = cntrl_count,
@@ -91,21 +96,21 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
                                       l2_select_num_bits = l2_bits,
                                       send_evictions = (
                                           options.cpu_type == "detailed"),
-                                      ruby_system = ruby_system)
+                                      prefetcher = prefetcher,
+                                      ruby_system = ruby_system,
+                                      enable_prefetch = False)
 
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,
                                 dcache = l1d_cache,
-                                physMemPort = system.physmem.port,
-                                physmem = system.physmem,
                                 ruby_system = ruby_system)
 
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
-        exec("system.l1_cntrl%d = l1_cntrl" % i)
+        exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
         
         #
         # Add controllers and sequencers to the appropriate lists
@@ -130,13 +135,13 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
                                       L2cacheMemory = l2_cache,
                                       ruby_system = ruby_system)
         
-        exec("system.l2_cntrl%d = l2_cntrl" % i)
+        exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
         l2_cntrl_nodes.append(l2_cntrl)
         
         cntrl_count += 1
-        
-    phys_mem_size = long(system.physmem.range.second) - \
-                      long(system.physmem.range.first) + 1
+
+    phys_mem_size = sum(map(lambda mem: mem.range.size(),
+                            system.memories.unproxy(system)))
     mem_module_size = phys_mem_size / options.num_dirs
 
     for i in xrange(options.num_dirs):
@@ -144,7 +149,8 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         # Create the Ruby objects associated with the directory controller
         #
 
-        mem_cntrl = RubyMemoryControl(version = i)
+        mem_cntrl = RubyMemoryControl(version = i,
+                                      ruby_system = ruby_system)
 
         dir_size = MemorySize('0B')
         dir_size.value = mem_module_size
@@ -153,22 +159,22 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
                                          cntrl_id = cntrl_count,
                                          directory = \
                                          RubyDirectoryMemory(version = i,
-                                                             size = dir_size),
+                                                             size = dir_size,
+                                                             use_map =
+                                                           options.use_map),
                                          memBuffer = mem_cntrl,
                                          ruby_system = ruby_system)
 
-        exec("system.dir_cntrl%d = dir_cntrl" % i)
+        exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
         dir_cntrl_nodes.append(dir_cntrl)
 
         cntrl_count += 1
 
-    for i, dma_device in enumerate(dma_devices):
+    for i, dma_port in enumerate(dma_ports):
         #
         # Create the Ruby objects associated with the dma controller
         #
         dma_seq = DMASequencer(version = i,
-                               physMemPort = system.physmem.port,
-                               physmem = system.physmem,
                                ruby_system = ruby_system)
         
         dma_cntrl = DMA_Controller(version = i,
@@ -176,13 +182,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
                                    dma_sequencer = dma_seq,
                                    ruby_system = ruby_system)
 
-        exec("system.dma_cntrl%d = dma_cntrl" % i)
-        if dma_device.type == 'MemTest':
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
-        else:
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+        exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
+        exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
         dma_cntrl_nodes.append(dma_cntrl)
-
         cntrl_count += 1
 
     all_cntrls = l1_cntrl_nodes + \
@@ -190,4 +192,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
                  dir_cntrl_nodes + \
                  dma_cntrl_nodes
 
-    return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
+    topology = create_topology(all_cntrls, options)
+
+    return (cpu_sequencers, dir_cntrl_nodes, topology)