import m5
from m5.objects import *
from m5.defines import buildEnv
-from m5.util import addToPath
+from Ruby import create_topology
#
# Note: the L1 Cache latency is only used by the sequencer on fast path hits
class L2Cache(RubyCache):
latency = 15
-def create_system(options, phys_mem, piobus, dma_devices):
+def define_options(parser):
+ return
+
+def create_system(options, system, piobus, dma_ports, ruby_system):
if buildEnv['PROTOCOL'] != 'MESI_CMP_directory':
panic("This script requires the MESI_CMP_directory protocol to be built.")
# Must create the individual controllers before the network to ensure the
# controller constructors are called before the network constructor
#
+ l2_bits = int(math.log(options.num_l2caches, 2))
+ block_size_bits = int(math.log(options.cacheline_size, 2))
+
+ cntrl_count = 0
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
l1i_cache = L1Cache(size = options.l1i_size,
- assoc = options.l1i_assoc)
+ assoc = options.l1i_assoc,
+ start_index_bit = block_size_bits,
+ is_icache = True)
l1d_cache = L1Cache(size = options.l1d_size,
- assoc = options.l1d_assoc)
-
- cpu_seq = RubySequencer(icache = l1i_cache,
- dcache = l1d_cache,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
+ assoc = options.l1d_assoc,
+ start_index_bit = block_size_bits,
+ is_icache = False)
- if piobus != None:
- cpu_seq.pio_port = piobus.port
+ prefetcher = RubyPrefetcher.Prefetcher()
l1_cntrl = L1Cache_Controller(version = i,
- sequencer = cpu_seq,
+ cntrl_id = cntrl_count,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
- l2_select_num_bits = \
- math.log(options.num_l2caches, 2))
+ l2_select_num_bits = l2_bits,
+ send_evictions = (
+ options.cpu_type == "detailed"),
+ prefetcher = prefetcher,
+ ruby_system = ruby_system,
+ enable_prefetch = False)
+
+ cpu_seq = RubySequencer(version = i,
+ icache = l1i_cache,
+ dcache = l1d_cache,
+ ruby_system = ruby_system)
+
+ l1_cntrl.sequencer = cpu_seq
+
+ if piobus != None:
+ cpu_seq.pio_port = piobus.slave
+
+ exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
+
#
# Add controllers and sequencers to the appropriate lists
#
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+
+ cntrl_count += 1
+
+ l2_index_start = block_size_bits + l2_bits
for i in xrange(options.num_l2caches):
#
# First create the Ruby objects associated with this cpu
#
l2_cache = L2Cache(size = options.l2_size,
- assoc = options.l2_assoc)
+ assoc = options.l2_assoc,
+ start_index_bit = l2_index_start)
l2_cntrl = L2Cache_Controller(version = i,
- L2cacheMemory = l2_cache)
+ cntrl_id = cntrl_count,
+ L2cacheMemory = l2_cache,
+ ruby_system = ruby_system)
+ exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
- phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
+ cntrl_count += 1
+
+ phys_mem_size = sum(map(lambda mem: mem.range.size(),
+ system.memories.unproxy(system)))
mem_module_size = phys_mem_size / options.num_dirs
for i in xrange(options.num_dirs):
# Create the Ruby objects associated with the directory controller
#
- mem_cntrl = RubyMemoryControl(version = i)
+ mem_cntrl = RubyMemoryControl(version = i,
+ ruby_system = ruby_system)
dir_size = MemorySize('0B')
dir_size.value = mem_module_size
dir_cntrl = Directory_Controller(version = i,
+ cntrl_id = cntrl_count,
directory = \
RubyDirectoryMemory(version = i,
- size = dir_size),
- memBuffer = mem_cntrl)
+ size = dir_size,
+ use_map =
+ options.use_map),
+ memBuffer = mem_cntrl,
+ ruby_system = ruby_system)
+ exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
- for i, dma_device in enumerate(dma_devices):
+ cntrl_count += 1
+
+ for i, dma_port in enumerate(dma_ports):
#
# Create the Ruby objects associated with the dma controller
#
dma_seq = DMASequencer(version = i,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
+ ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,
- dma_sequencer = dma_seq)
+ cntrl_id = cntrl_count,
+ dma_sequencer = dma_seq,
+ ruby_system = ruby_system)
- dma_cntrl.dma_sequencer.port = dma_device.dma
+ exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
+ exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
+ cntrl_count += 1
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \
dir_cntrl_nodes + \
dma_cntrl_nodes
- return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
+ topology = create_topology(all_cntrls, options)
+
+ return (cpu_sequencers, dir_cntrl_nodes, topology)
projects / gem5.git / blobdiff