def define_options(parser):
return
-def create_system(options, system, piobus, dma_ports, ruby_system):
+def create_system(options, system, dma_ports, ruby_system):
if buildEnv['PROTOCOL'] != 'MI_example':
panic("This script requires the MI_example protocol to be built.")
#
block_size_bits = int(math.log(options.cacheline_size, 2))
- cntrl_count = 0
-
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
# Only one unified L1 cache exists. Can cache instructions and data.
#
l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
cacheMemory = cache,
send_evictions = (
options.cpu_type == "detailed"),
+ transitions_per_cycle = options.ports,
+ clk_domain=system.cpu[i].clk_domain,
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i,
icache = cache,
dcache = cache,
+ clk_domain=system.cpu[i].clk_domain,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq
-
- if piobus != None:
- cpu_seq.pio_port = piobus.slave
-
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
- #
+
# Add controllers and sequencers to the appropriate lists
- #
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
- cntrl_count += 1
+ # Connect the L1 controllers and the network
+ l1_cntrl.requestFromCache = ruby_system.network.slave
+ l1_cntrl.responseFromCache = ruby_system.network.slave
+ l1_cntrl.forwardToCache = ruby_system.network.master
+ l1_cntrl.responseToCache = ruby_system.network.master
+
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
dir_size.value = mem_module_size
dir_cntrl = Directory_Controller(version = i,
- cntrl_id = cntrl_count,
directory = \
RubyDirectoryMemory( \
version = i,
map_levels = \
options.map_levels),
memBuffer = mem_cntrl,
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
- cntrl_count += 1
+ # Connect the directory controllers and the network
+ dir_cntrl.requestToDir = ruby_system.network.master
+ dir_cntrl.dmaRequestToDir = ruby_system.network.master
+
+ dir_cntrl.responseFromDir = ruby_system.network.slave
+ dir_cntrl.dmaResponseFromDir = ruby_system.network.slave
+ dir_cntrl.forwardFromDir = ruby_system.network.slave
+
for i, dma_port in enumerate(dma_ports):
#
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,
- cntrl_id = cntrl_count,
dma_sequencer = dma_seq,
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
- cntrl_count += 1
- all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
+ # Connect the directory controllers and the network
+ dma_cntrl.requestToDir = ruby_system.network.master
+ dma_cntrl.responseFromDir = ruby_system.network.slave
- topology = create_topology(all_cntrls, options)
+ all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
+ topology = create_topology(all_cntrls, options)
return (cpu_sequencers, dir_cntrl_nodes, topology)