#
# Authors: Brad Beckmann
+import math
import m5
from m5.objects import *
from m5.defines import buildEnv
-from m5.util import addToPath
+from Ruby import create_topology
#
# Note: the cache latency is only used by the sequencer on fast path hits
class Cache(RubyCache):
latency = 3
-def create_system(options, phys_mem, piobus, dma_devices):
+def define_options(parser):
+ return
+
+def create_system(options, system, dma_ports, ruby_system):
if buildEnv['PROTOCOL'] != 'MI_example':
panic("This script requires the MI_example protocol to be built.")
# Must create the individual controllers before the network to ensure the
# controller constructors are called before the network constructor
#
-
+ block_size_bits = int(math.log(options.cacheline_size, 2))
+
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
# config parameters.
#
cache = Cache(size = options.l1d_size,
- assoc = options.l1d_assoc)
+ assoc = options.l1d_assoc,
+ start_index_bit = block_size_bits)
#
# Only one unified L1 cache exists. Can cache instructions and data.
#
- cpu_seq = RubySequencer(icache = cache,
+ l1_cntrl = L1Cache_Controller(version = i,
+ cacheMemory = cache,
+ send_evictions = (
+ options.cpu_type == "detailed"),
+ transitions_per_cycle = options.ports,
+ clk_domain=system.cpu[i].clk_domain,
+ ruby_system = ruby_system)
+
+ cpu_seq = RubySequencer(version = i,
+ icache = cache,
dcache = cache,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
+ clk_domain=system.cpu[i].clk_domain,
+ ruby_system = ruby_system)
- if piobus != None:
- cpu_seq.pio_port = piobus.port
+ l1_cntrl.sequencer = cpu_seq
+ exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
- l1_cntrl = L1Cache_Controller(version = i,
- sequencer = cpu_seq,
- cacheMemory = cache)
- #
# Add controllers and sequencers to the appropriate lists
- #
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
- phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
+ # Connect the L1 controllers and the network
+ l1_cntrl.requestFromCache = ruby_system.network.slave
+ l1_cntrl.responseFromCache = ruby_system.network.slave
+ l1_cntrl.forwardToCache = ruby_system.network.master
+ l1_cntrl.responseToCache = ruby_system.network.master
+
+
+ phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
+ assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
+ # Run each of the ruby memory controllers at a ratio of the frequency of
+ # the ruby system.
+ # clk_divider value is a fix to pass regression.
+ ruby_system.memctrl_clk_domain = DerivedClockDomain(
+ clk_domain=ruby_system.clk_domain,
+ clk_divider=3)
+
for i in xrange(options.num_dirs):
#
# Create the Ruby objects associated with the directory controller
#
- mem_cntrl = RubyMemoryControl(version = i)
+ mem_cntrl = RubyMemoryControl(
+ clk_domain = ruby_system.memctrl_clk_domain,
+ version = i,
+ ruby_system = ruby_system)
dir_size = MemorySize('0B')
dir_size.value = mem_module_size
dir_cntrl = Directory_Controller(version = i,
directory = \
- RubyDirectoryMemory(version = i,
- size = dir_size),
- memBuffer = mem_cntrl)
-
+ RubyDirectoryMemory( \
+ version = i,
+ size = dir_size,
+ use_map = options.use_map,
+ map_levels = \
+ options.map_levels),
+ memBuffer = mem_cntrl,
+ transitions_per_cycle = options.ports,
+ ruby_system = ruby_system)
+
+ exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
- for i, dma_device in enumerate(dma_devices):
+ # Connect the directory controllers and the network
+ dir_cntrl.requestToDir = ruby_system.network.master
+ dir_cntrl.dmaRequestToDir = ruby_system.network.master
+
+ dir_cntrl.responseFromDir = ruby_system.network.slave
+ dir_cntrl.dmaResponseFromDir = ruby_system.network.slave
+ dir_cntrl.forwardFromDir = ruby_system.network.slave
+
+
+ for i, dma_port in enumerate(dma_ports):
#
# Create the Ruby objects associated with the dma controller
#
dma_seq = DMASequencer(version = i,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
+ ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,
- dma_sequencer = dma_seq)
+ dma_sequencer = dma_seq,
+ transitions_per_cycle = options.ports,
+ ruby_system = ruby_system)
- dma_cntrl.dma_sequencer.port = dma_device.dma
+ exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
+ exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
- all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
+ # Connect the directory controllers and the network
+ dma_cntrl.requestToDir = ruby_system.network.master
+ dma_cntrl.responseFromDir = ruby_system.network.slave
- return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
+
+ all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
+ topology = create_topology(all_cntrls, options)
+ return (cpu_sequencers, dir_cntrl_nodes, topology)
projects / gem5.git / blobdiff