def define_options(parser):
return
-def create_system(options, system, piobus, dma_ports, ruby_system):
+def create_system(options, system, dma_ports, ruby_system):
if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
panic("This script requires the MOESI_CMP_directory protocol to be built.")
l2_bits = int(math.log(options.num_l2caches, 2))
block_size_bits = int(math.log(options.cacheline_size, 2))
- cntrl_count = 0
-
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
l1i_cache = L1Cache(size = options.l1i_size,
assoc = options.l1i_assoc,
- start_index_bit = block_size_bits)
+ start_index_bit = block_size_bits,
+ is_icache = True)
l1d_cache = L1Cache(size = options.l1d_size,
assoc = options.l1d_assoc,
- start_index_bit = block_size_bits)
+ start_index_bit = block_size_bits,
+ is_icache = False)
l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
+ L1Icache = l1i_cache,
+ L1Dcache = l1d_cache,
l2_select_num_bits = l2_bits,
send_evictions = (
options.cpu_type == "detailed"),
+ transitions_per_cycle = options.ports,
+ clk_domain=system.cpu[i].clk_domain,
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
+ clk_domain=system.cpu[i].clk_domain,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq
+ exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
- if piobus != None:
- cpu_seq.pio_port = piobus.slave
-
- exec("system.l1_cntrl%d = l1_cntrl" % i)
- #
# Add controllers and sequencers to the appropriate lists
- #
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
- cntrl_count += 1
+ # Connect the L1 controllers and the network
+ l1_cntrl.requestFromL1Cache = ruby_system.network.slave
+ l1_cntrl.responseFromL1Cache = ruby_system.network.slave
+ l1_cntrl.requestToL1Cache = ruby_system.network.master
+ l1_cntrl.responseToL1Cache = ruby_system.network.master
+
l2_index_start = block_size_bits + l2_bits
start_index_bit = l2_index_start)
l2_cntrl = L2Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- L2cacheMemory = l2_cache,
+ L2cache = l2_cache,
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
- exec("system.l2_cntrl%d = l2_cntrl" % i)
+ exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
- cntrl_count += 1
-
- phys_mem_size = 0
- for mem in system.memories.unproxy(system):
- phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
+ # Connect the L2 controllers and the network
+ l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.responseFromL2Cache = ruby_system.network.slave
+
+ l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master
+ l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
+ l2_cntrl.responseToL2Cache = ruby_system.network.master
+
+
+ phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
+ assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
+
+ # Run each of the ruby memory controllers at a ratio of the frequency of
+ # the ruby system.
+ # clk_divider value is a fix to pass regression.
+ ruby_system.memctrl_clk_domain = DerivedClockDomain(
+ clk_domain=ruby_system.clk_domain,
+ clk_divider=3)
+
for i in xrange(options.num_dirs):
#
# Create the Ruby objects associated with the directory controller
#
- mem_cntrl = RubyMemoryControl(version = i,
- ruby_system = ruby_system)
+ mem_cntrl = RubyMemoryControl(
+ clk_domain = ruby_system.memctrl_clk_domain,
+ version = i,
+ ruby_system = ruby_system)
dir_size = MemorySize('0B')
dir_size.value = mem_module_size
dir_cntrl = Directory_Controller(version = i,
- cntrl_id = cntrl_count,
directory = \
RubyDirectoryMemory(version = i,
- size = dir_size),
+ size = dir_size,
+ use_map = options.use_map),
memBuffer = mem_cntrl,
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
- exec("system.dir_cntrl%d = dir_cntrl" % i)
+ exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
- cntrl_count += 1
+ # Connect the directory controllers and the network
+ dir_cntrl.requestToDir = ruby_system.network.master
+ dir_cntrl.responseToDir = ruby_system.network.master
+ dir_cntrl.responseFromDir = ruby_system.network.slave
+ dir_cntrl.forwardFromDir = ruby_system.network.slave
+
for i, dma_port in enumerate(dma_ports):
#
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,
- cntrl_id = cntrl_count,
dma_sequencer = dma_seq,
+ transitions_per_cycle = options.ports,
ruby_system = ruby_system)
- exec("system.dma_cntrl%d = dma_cntrl" % i)
- exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
+ exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
+ exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
- cntrl_count += 1
+
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \
dma_cntrl_nodes
topology = create_topology(all_cntrls, options)
-
return (cpu_sequencers, dir_cntrl_nodes, topology)
projects / gem5.git / blobdiff