import m5
from m5.objects import *
from m5.defines import buildEnv
-from m5.util import addToPath
#
# Note: the L1 Cache latency is only used by the sequencer on fast path hits
#
class L1Cache(RubyCache):
- latency = 3
+ latency = 2
#
# Note: the L2 Cache latency is not currently used
#
class L2Cache(RubyCache):
- latency = 15
-
-def create_system(options, phys_mem, piobus, dma_devices):
+ latency = 10
+
+def define_options(parser):
+ parser.add_option("--l1-retries", type="int", default=1,
+ help="Token_CMP: # of l1 retries before going persistent")
+ parser.add_option("--timeout-latency", type="int", default=300,
+ help="Token_CMP: cycles until issuing again");
+ parser.add_option("--disable-dyn-timeouts", action="store_true",
+ help="Token_CMP: disable dyanimc timeouts, use fixed latency instead")
+ parser.add_option("--allow-atomic-migration", action="store_true",
+ help="allow migratory sharing for atomic only accessed blocks")
+
+def create_system(options, system, piobus, dma_devices, ruby_system):
if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
panic("This script requires the MOESI_CMP_token protocol to be built.")
# Must create the individual controllers before the network to ensure the
# controller constructors are called before the network constructor
#
+ l2_bits = int(math.log(options.num_l2caches, 2))
+ block_size_bits = int(math.log(options.cacheline_size, 2))
+ cntrl_count = 0
+
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
l1i_cache = L1Cache(size = options.l1i_size,
- assoc = options.l1i_assoc)
+ assoc = options.l1i_assoc,
+ start_index_bit = block_size_bits)
l1d_cache = L1Cache(size = options.l1d_size,
- assoc = options.l1d_assoc)
+ assoc = options.l1d_assoc,
+ start_index_bit = block_size_bits)
- cpu_seq = RubySequencer(icache = l1i_cache,
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ l2_select_num_bits = l2_bits,
+ N_tokens = n_tokens,
+ retry_threshold = \
+ options.l1_retries,
+ fixed_timeout_latency = \
+ options.timeout_latency,
+ dynamic_timeout_enabled = \
+ not options.disable_dyn_timeouts,
+ no_mig_atomic = not \
+ options.allow_atomic_migration,
+ ruby_system = ruby_system)
+
+ cpu_seq = RubySequencer(version = i,
+ icache = l1i_cache,
dcache = l1d_cache,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
+ physMemPort = system.physmem.port,
+ physmem = system.physmem,
+ ruby_system = ruby_system)
+
+ l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- l2_select_num_bits = \
- math.log(options.num_l2caches, 2),
- N_tokens = n_tokens)
+ exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
#
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ cntrl_count += 1
+
+ l2_index_start = block_size_bits + l2_bits
+
for i in xrange(options.num_l2caches):
#
# First create the Ruby objects associated with this cpu
#
l2_cache = L2Cache(size = options.l2_size,
- assoc = options.l2_assoc)
+ assoc = options.l2_assoc,
+ start_index_bit = l2_index_start)
l2_cntrl = L2Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
L2cacheMemory = l2_cache,
- N_tokens = n_tokens)
+ N_tokens = n_tokens,
+ ruby_system = ruby_system)
+ exec("system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
+
+ cntrl_count += 1
- phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
+ phys_mem_size = long(system.physmem.range.second) - \
+ long(system.physmem.range.first) + 1
mem_module_size = phys_mem_size / options.num_dirs
for i in xrange(options.num_dirs):
dir_size.value = mem_module_size
dir_cntrl = Directory_Controller(version = i,
+ cntrl_id = cntrl_count,
directory = \
RubyDirectoryMemory(version = i,
size = dir_size),
memBuffer = mem_cntrl,
- l2_select_num_bits = \
- math.log(options.num_l2caches, 2))
+ l2_select_num_bits = l2_bits,
+ ruby_system = ruby_system)
+ exec("system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
+ cntrl_count += 1
+
for i, dma_device in enumerate(dma_devices):
#
# Create the Ruby objects associated with the dma controller
#
dma_seq = DMASequencer(version = i,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
+ physMemPort = system.physmem.port,
+ physmem = system.physmem,
+ ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,
- dma_sequencer = dma_seq)
-
- dma_cntrl.dma_sequencer.port = dma_device.dma
+ cntrl_id = cntrl_count,
+ dma_sequencer = dma_seq,
+ ruby_system = ruby_system)
+
+ exec("system.dma_cntrl%d = dma_cntrl" % i)
+ if dma_device.type == 'MemTest':
+ exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+ else:
+ exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
+ cntrl_count += 1
+
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \
dir_cntrl_nodes + \
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