MEM: Separate queries for snooping and address ranges

[gem5.git] / configs / ruby / MOESI_CMP_token.py

diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py
index ba61c727a60f290e251f5dfcebe67083a251f6b5..d11bb320c6d70af2908f34e949476cf36026e81d 100644 (file)
--- a/configs/ruby/MOESI_CMP_token.py
+++ b/configs/ruby/MOESI_CMP_token.py
@@ -54,7 +54,7 @@ def define_options(parser):
     parser.add_option("--allow-atomic-migration", action="store_true",
           help="allow migratory sharing for atomic only accessed blocks")
     
-def create_system(options, system, piobus, dma_devices):
+def create_system(options, system, piobus, dma_devices, ruby_system):
     
     if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
         panic("This script requires the MOESI_CMP_token protocol to be built.")
@@ -82,27 +82,23 @@ def create_system(options, system, piobus, dma_devices):
     # controller constructors are called before the network constructor
     #
     l2_bits = int(math.log(options.num_l2caches, 2))
+    block_size_bits = int(math.log(options.cacheline_size, 2))
     
+    cntrl_count = 0
+
     for i in xrange(options.num_cpus):
         #
         # First create the Ruby objects associated with this cpu
         #
         l1i_cache = L1Cache(size = options.l1i_size,
-                            assoc = options.l1i_assoc)
+                            assoc = options.l1i_assoc,
+                            start_index_bit = block_size_bits)
         l1d_cache = L1Cache(size = options.l1d_size,
-                            assoc = options.l1d_assoc)
-
-        cpu_seq = RubySequencer(version = i,
-                                icache = l1i_cache,
-                                dcache = l1d_cache,
-                                physMemPort = system.physmem.port,
-                                physmem = system.physmem)
-
-        if piobus != None:
-            cpu_seq.pio_port = piobus.port
+                            assoc = options.l1d_assoc,
+                            start_index_bit = block_size_bits)
 
         l1_cntrl = L1Cache_Controller(version = i,
-                                      sequencer = cpu_seq,
+                                      cntrl_id = cntrl_count,
                                       L1IcacheMemory = l1i_cache,
                                       L1DcacheMemory = l1d_cache,
                                       l2_select_num_bits = l2_bits,
@@ -114,7 +110,20 @@ def create_system(options, system, piobus, dma_devices):
                                       dynamic_timeout_enabled = \
                                         not options.disable_dyn_timeouts,
                                       no_mig_atomic = not \
-                                        options.allow_atomic_migration)
+                                        options.allow_atomic_migration,
+                                      ruby_system = ruby_system)
+
+        cpu_seq = RubySequencer(version = i,
+                                icache = l1i_cache,
+                                dcache = l1d_cache,
+                                physMemPort = system.physmem.port,
+                                physmem = system.physmem,
+                                ruby_system = ruby_system)
+
+        l1_cntrl.sequencer = cpu_seq
+
+        if piobus != None:
+            cpu_seq.pio_port = piobus.port
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         #
@@ -123,20 +132,28 @@ def create_system(options, system, piobus, dma_devices):
         cpu_sequencers.append(cpu_seq)
         l1_cntrl_nodes.append(l1_cntrl)
 
+        cntrl_count += 1
+
+    l2_index_start = block_size_bits + l2_bits
+
     for i in xrange(options.num_l2caches):
         #
         # First create the Ruby objects associated with this cpu
         #
         l2_cache = L2Cache(size = options.l2_size,
                            assoc = options.l2_assoc,
-                           start_index_bit = l2_bits)
+                           start_index_bit = l2_index_start)
 
         l2_cntrl = L2Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
                                       L2cacheMemory = l2_cache,
-                                      N_tokens = n_tokens)
+                                      N_tokens = n_tokens,
+                                      ruby_system = ruby_system)
         
         exec("system.l2_cntrl%d = l2_cntrl" % i)
         l2_cntrl_nodes.append(l2_cntrl)
+
+        cntrl_count += 1
         
     phys_mem_size = long(system.physmem.range.second) - \
                       long(system.physmem.range.first) + 1
@@ -153,37 +170,42 @@ def create_system(options, system, piobus, dma_devices):
         dir_size.value = mem_module_size
 
         dir_cntrl = Directory_Controller(version = i,
+                                         cntrl_id = cntrl_count,
                                          directory = \
                                          RubyDirectoryMemory(version = i,
-                                                             size = \
-                                                               dir_size),
+                                                             size = dir_size),
                                          memBuffer = mem_cntrl,
-                                         l2_select_num_bits = \
-                                           math.log(options.num_l2caches,
-                                                    2))
+                                         l2_select_num_bits = l2_bits,
+                                         ruby_system = ruby_system)
 
         exec("system.dir_cntrl%d = dir_cntrl" % i)
         dir_cntrl_nodes.append(dir_cntrl)
 
+        cntrl_count += 1
+
     for i, dma_device in enumerate(dma_devices):
         #
         # Create the Ruby objects associated with the dma controller
         #
         dma_seq = DMASequencer(version = i,
                                physMemPort = system.physmem.port,
-                               physmem = system.physmem)
+                               physmem = system.physmem,
+                               ruby_system = ruby_system)
         
         dma_cntrl = DMA_Controller(version = i,
-                                   dma_sequencer = dma_seq)
+                                   cntrl_id = cntrl_count,
+                                   dma_sequencer = dma_seq,
+                                   ruby_system = ruby_system)
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            system.dma_cntrl.dma_sequencer.port = dma_device.test
+            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
         else:
-            system.dma_cntrl.dma_sequencer.port = dma_device.dma
-        dma_cntrl.dma_sequencer.port = dma_device.dma
+            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
+        cntrl_count += 1
+
     all_cntrls = l1_cntrl_nodes + \
                  l2_cntrl_nodes + \
                  dir_cntrl_nodes + \