import m5
from m5.objects import *
from m5.defines import buildEnv
+from Ruby import create_topology
#
# Note: the L1 Cache latency is only used by the sequencer on fast path hits
#
class L1Cache(RubyCache):
- latency = 3
+ latency = 2
#
# Note: the L2 Cache latency is not currently used
#
class L2Cache(RubyCache):
- latency = 15
+ latency = 10
def define_options(parser):
parser.add_option("--l1-retries", type="int", default=1,
help="Token_CMP: cycles until issuing again");
parser.add_option("--disable-dyn-timeouts", action="store_true",
help="Token_CMP: disable dyanimc timeouts, use fixed latency instead")
-
-def create_system(options, system, piobus, dma_devices):
+ parser.add_option("--allow-atomic-migration", action="store_true",
+ help="allow migratory sharing for atomic only accessed blocks")
+
+def create_system(options, system, dma_ports, ruby_system):
if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
panic("This script requires the MOESI_CMP_token protocol to be built.")
# Must create the individual controllers before the network to ensure the
# controller constructors are called before the network constructor
#
+ l2_bits = int(math.log(options.num_l2caches, 2))
+ block_size_bits = int(math.log(options.cacheline_size, 2))
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
l1i_cache = L1Cache(size = options.l1i_size,
- assoc = options.l1i_assoc)
+ assoc = options.l1i_assoc,
+ start_index_bit = block_size_bits)
l1d_cache = L1Cache(size = options.l1d_size,
- assoc = options.l1d_assoc)
-
- cpu_seq = RubySequencer(version = i,
- icache = l1i_cache,
- dcache = l1d_cache,
- physMemPort = system.physmem.port,
- physmem = system.physmem)
-
- if piobus != None:
- cpu_seq.pio_port = piobus.port
+ assoc = options.l1d_assoc,
+ start_index_bit = block_size_bits)
l1_cntrl = L1Cache_Controller(version = i,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- l2_select_num_bits = \
- math.log(options.num_l2caches,
- 2),
+ L1Icache = l1i_cache,
+ L1Dcache = l1d_cache,
+ l2_select_num_bits = l2_bits,
N_tokens = n_tokens,
retry_threshold = \
options.l1_retries,
fixed_timeout_latency = \
options.timeout_latency,
dynamic_timeout_enabled = \
- not options.disable_dyn_timeouts)
+ not options.disable_dyn_timeouts,
+ no_mig_atomic = not \
+ options.allow_atomic_migration,
+ send_evictions = (
+ options.cpu_type == "detailed"),
+ transitions_per_cycle = options.ports,
+ clk_domain=system.cpu[i].clk_domain,
+ ruby_system = ruby_system)
+
+ cpu_seq = RubySequencer(version = i,
+ icache = l1i_cache,
+ dcache = l1d_cache,
+ clk_domain=system.cpu[i].clk_domain,
+ ruby_system = ruby_system)
+
+ l1_cntrl.sequencer = cpu_seq
+ exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
- exec("system.l1_cntrl%d = l1_cntrl" % i)
- #
# Add controllers and sequencers to the appropriate lists
- #
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ # Connect the L1 controllers and the network
+ l1_cntrl.requestFromL1Cache = ruby_system.network.slave
+ l1_cntrl.responseFromL1Cache = ruby_system.network.slave
+ l1_cntrl.persistentFromL1Cache = ruby_system.network.slave
+
+ l1_cntrl.requestToL1Cache = ruby_system.network.master
+ l1_cntrl.responseToL1Cache = ruby_system.network.master
+ l1_cntrl.persistentToL1Cache = ruby_system.network.master
+
+
+ l2_index_start = block_size_bits + l2_bits
+
for i in xrange(options.num_l2caches):
#
# First create the Ruby objects associated with this cpu
#
l2_cache = L2Cache(size = options.l2_size,
- assoc = options.l2_assoc)
+ assoc = options.l2_assoc,
+ start_index_bit = l2_index_start)
l2_cntrl = L2Cache_Controller(version = i,
- L2cacheMemory = l2_cache,
- N_tokens = n_tokens)
+ L2cache = l2_cache,
+ N_tokens = n_tokens,
+ transitions_per_cycle = options.ports,
+ ruby_system = ruby_system)
- exec("system.l2_cntrl%d = l2_cntrl" % i)
+ exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
-
- phys_mem_size = long(system.physmem.range.second) - \
- long(system.physmem.range.first) + 1
+
+ # Connect the L2 controllers and the network
+ l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.responseFromL2Cache = ruby_system.network.slave
+
+ l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master
+ l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
+ l2_cntrl.responseToL2Cache = ruby_system.network.master
+ l2_cntrl.persistentToL2Cache = ruby_system.network.master
+
+
+ phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
+ assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
+ # Run each of the ruby memory controllers at a ratio of the frequency of
+ # the ruby system
+ # clk_divider value is a fix to pass regression.
+ ruby_system.memctrl_clk_domain = DerivedClockDomain(
+ clk_domain=ruby_system.clk_domain,
+ clk_divider=3)
+
for i in xrange(options.num_dirs):
#
# Create the Ruby objects associated with the directory controller
#
- mem_cntrl = RubyMemoryControl(version = i)
+ mem_cntrl = RubyMemoryControl(
+ clk_domain = ruby_system.memctrl_clk_domain,
+ version = i,
+ ruby_system = ruby_system)
dir_size = MemorySize('0B')
dir_size.value = mem_module_size
dir_cntrl = Directory_Controller(version = i,
directory = \
RubyDirectoryMemory(version = i,
- size = \
- dir_size),
+ use_map = options.use_map,
+ size = dir_size),
memBuffer = mem_cntrl,
- l2_select_num_bits = \
- math.log(options.num_l2caches,
- 2))
+ l2_select_num_bits = l2_bits,
+ transitions_per_cycle = options.ports,
+ ruby_system = ruby_system)
- exec("system.dir_cntrl%d = dir_cntrl" % i)
+ exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
- for i, dma_device in enumerate(dma_devices):
+ # Connect the directory controllers and the network
+ dir_cntrl.requestToDir = ruby_system.network.master
+ dir_cntrl.responseToDir = ruby_system.network.master
+ dir_cntrl.persistentToDir = ruby_system.network.master
+ dir_cntrl.dmaRequestToDir = ruby_system.network.master
+
+ dir_cntrl.requestFromDir = ruby_system.network.slave
+ dir_cntrl.responseFromDir = ruby_system.network.slave
+ dir_cntrl.persistentFromDir = ruby_system.network.slave
+ dir_cntrl.dmaResponseFromDir = ruby_system.network.slave
+
+
+ for i, dma_port in enumerate(dma_ports):
#
# Create the Ruby objects associated with the dma controller
#
dma_seq = DMASequencer(version = i,
- physMemPort = system.physmem.port,
- physmem = system.physmem)
+ ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,
- dma_sequencer = dma_seq)
+ dma_sequencer = dma_seq,
+ transitions_per_cycle = options.ports,
+ ruby_system = ruby_system)
- exec("system.dma_cntrl%d = dma_cntrl" % i)
- dma_cntrl.dma_sequencer.port = dma_device.dma
+ exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
+ exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
all_cntrls = l1_cntrl_nodes + \
dir_cntrl_nodes + \
dma_cntrl_nodes
- return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
+ topology = create_topology(all_cntrls, options)
+
+ return (cpu_sequencers, dir_cntrl_nodes, topology)
projects / gem5.git / blobdiff