Ruby: Add support for functional accesses

[gem5.git] / configs / ruby / MOESI_hammer.py

diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index 3cd33f9816679329d4d4a618014e2a437df51ad0..6e46f3e0f0a1ec9215a1d7055392c697989ba078 100644 (file)
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -55,9 +55,11 @@ def define_options(parser):
           help="allow migratory sharing for atomic only accessed blocks")
     parser.add_option("--pf-on", action="store_true",
           help="Hammer: enable Probe Filter")
-    
-def create_system(options, system, piobus, dma_devices):
-    
+    parser.add_option("--dir-on", action="store_true",
+          help="Hammer: enable Full-bit Directory")
+
+def create_system(options, system, piobus, dma_devices, ruby_system):
+
     if buildEnv['PROTOCOL'] != 'MOESI_hammer':
         panic("This script requires the MOESI_hammer protocol to be built.")
 
@@ -76,35 +78,45 @@ def create_system(options, system, piobus, dma_devices):
     # Must create the individual controllers before the network to ensure the
     # controller constructors are called before the network constructor
     #
+    block_size_bits = int(math.log(options.cacheline_size, 2))
+
+    cntrl_count = 0
     
     for i in xrange(options.num_cpus):
         #
         # First create the Ruby objects associated with this cpu
         #
         l1i_cache = L1Cache(size = options.l1i_size,
-                            assoc = options.l1i_assoc)
+                            assoc = options.l1i_assoc,
+                            start_index_bit = block_size_bits)
         l1d_cache = L1Cache(size = options.l1d_size,
-                            assoc = options.l1d_assoc)
+                            assoc = options.l1d_assoc,
+                            start_index_bit = block_size_bits)
         l2_cache = L2Cache(size = options.l2_size,
-                           assoc = options.l2_assoc)
+                           assoc = options.l2_assoc,
+                           start_index_bit = block_size_bits)
+
+        l1_cntrl = L1Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
+                                      L1IcacheMemory = l1i_cache,
+                                      L1DcacheMemory = l1d_cache,
+                                      L2cacheMemory = l2_cache,
+                                      no_mig_atomic = not \
+                                        options.allow_atomic_migration,
+                                      ruby_system = ruby_system)
 
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,
                                 dcache = l1d_cache,
                                 physMemPort = system.physmem.port,
-                                physmem = system.physmem)
+                                physmem = system.physmem,
+                                ruby_system = ruby_system)
+
+        l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
             cpu_seq.pio_port = piobus.port
 
-        l1_cntrl = L1Cache_Controller(version = i,
-                                      sequencer = cpu_seq,
-                                      L1IcacheMemory = l1i_cache,
-                                      L1DcacheMemory = l1d_cache,
-                                      L2cacheMemory = l2_cache,
-                                      no_mig_atomic = not \
-                                        options.allow_atomic_migration)
-
         if options.recycle_latency:
             l1_cntrl.recycle_latency = options.recycle_latency
 
@@ -115,6 +127,8 @@ def create_system(options, system, piobus, dma_devices):
         cpu_sequencers.append(cpu_seq)
         l1_cntrl_nodes.append(l1_cntrl)
 
+        cntrl_count += 1
+
     phys_mem_size = long(system.physmem.range.second) - \
                       long(system.physmem.range.first) + 1
     mem_module_size = phys_mem_size / options.num_dirs
@@ -152,20 +166,25 @@ def create_system(options, system, piobus, dma_devices):
         dir_size = MemorySize('0B')
         dir_size.value = mem_module_size
 
-        pf = ProbeFilter(size = pf_size, assoc = 4)
+        pf = ProbeFilter(size = pf_size, assoc = 4,
+                         start_index_bit = pf_start_bit)
 
         dir_cntrl = Directory_Controller(version = i,
+                                         cntrl_id = cntrl_count,
                                          directory = \
                                          RubyDirectoryMemory( \
                                                     version = i,
                                                     size = dir_size,
                                                     use_map = options.use_map,
                                                     map_levels = \
-                                                    options.map_levels),
+                                                    options.map_levels,
+                                                    numa_high_bit = \
+                                                      options.numa_high_bit),
                                          probeFilter = pf,
                                          memBuffer = mem_cntrl,
-                                         probe_filter_enabled = \
-                                           options.pf_on)
+                                         probe_filter_enabled = options.pf_on,
+                                         full_bit_dir_enabled = options.dir_on,
+                                         ruby_system = ruby_system)
 
         if options.recycle_latency:
             dir_cntrl.recycle_latency = options.recycle_latency
@@ -173,6 +192,8 @@ def create_system(options, system, piobus, dma_devices):
         exec("system.dir_cntrl%d = dir_cntrl" % i)
         dir_cntrl_nodes.append(dir_cntrl)
 
+        cntrl_count += 1
+
     for i, dma_device in enumerate(dma_devices):
         #
         # Create the Ruby objects associated with the dma controller
@@ -182,19 +203,21 @@ def create_system(options, system, piobus, dma_devices):
                                physmem = system.physmem)
         
         dma_cntrl = DMA_Controller(version = i,
+                                   cntrl_id = cntrl_count,
                                    dma_sequencer = dma_seq)
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            system.dma_cntrl.dma_sequencer.port = dma_device.test
+            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
         else:
-            system.dma_cntrl.dma_sequencer.port = dma_device.dma
-        dma_cntrl.dma_sequencer.port = dma_device.dma
+            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
         if options.recycle_latency:
             dma_cntrl.recycle_latency = options.recycle_latency
 
+        cntrl_count += 1
+
     all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
 
     return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)