architecture behave of core is
-- fetch signals
- signal fetch1_to_fetch2: Fetch1ToFetch2Type;
signal fetch2_to_decode1: Fetch2ToDecode1Type;
-- icache signals
- signal fetch2_to_icache : Fetch2ToIcacheType;
+ signal fetch1_to_icache : Fetch1ToIcacheType;
signal icache_to_fetch2 : IcacheToFetch2Type;
-- decode signals
signal writeback_to_cr_file: WritebackToCrFileType;
-- execute signals
- signal execute1_to_execute2: Execute1ToExecute2Type;
- signal execute2_to_writeback: Execute2ToWritebackType;
+ signal execute1_to_writeback: Execute1ToWritebackType;
signal execute1_to_fetch1: Execute1ToFetch1Type;
-- load store signals
signal decode2_to_multiply: Decode2ToMultiplyType;
signal multiply_to_writeback: MultiplyToWritebackType;
+ -- divider signals
+ signal decode2_to_divider: Decode2ToDividerType;
+ signal divider_to_writeback: DividerToWritebackType;
+
-- local signals
signal fetch1_stall_in : std_ulogic;
+ signal icache_stall_out : std_ulogic;
signal fetch2_stall_in : std_ulogic;
- signal fetch2_stall_out : std_ulogic;
signal decode1_stall_in : std_ulogic;
signal decode2_stall_out : std_ulogic;
-- Debug status
signal dbg_core_is_stopped: std_ulogic;
- -- For sim
- signal registers: regfile;
-
begin
core_rst <= dbg_core_rst or rst;
rst => core_rst,
stall_in => fetch1_stall_in,
flush_in => flush,
- e_in => execute1_to_fetch1,
- f_out => fetch1_to_fetch2
- );
-
- fetch1_stall_in <= fetch2_stall_out or decode2_stall_out;
-
- fetch2_0: entity work.fetch2
- port map (
- clk => clk,
- rst => core_rst,
- stall_in => fetch2_stall_in,
- stall_out => fetch2_stall_out,
- flush_in => flush,
- i_in => icache_to_fetch2,
- i_out => fetch2_to_icache,
stop_in => dbg_core_stop,
- f_in => fetch1_to_fetch2,
- f_out => fetch2_to_decode1
+ e_in => execute1_to_fetch1,
+ i_out => fetch1_to_icache
);
- fetch2_stall_in <= decode2_stall_out;
+ fetch1_stall_in <= icache_stall_out or decode2_stall_out;
icache_0: entity work.icache
generic map(
- LINE_SIZE_DW => 8,
- NUM_LINES => 16
+ LINE_SIZE => 64,
+ NUM_LINES => 16,
+ NUM_WAYS => 2
)
port map(
clk => clk,
rst => icache_rst,
- i_in => fetch2_to_icache,
+ i_in => fetch1_to_icache,
i_out => icache_to_fetch2,
+ flush_in => flush,
+ stall_out => icache_stall_out,
wishbone_out => wishbone_insn_out,
wishbone_in => wishbone_insn_in
);
- icache_rst <= rst or dbg_icache_rst;
+ icache_rst <= rst or dbg_icache_rst;
+
+ fetch2_0: entity work.fetch2
+ port map (
+ clk => clk,
+ rst => core_rst,
+ stall_in => fetch2_stall_in,
+ flush_in => flush,
+ i_in => icache_to_fetch2,
+ f_out => fetch2_to_decode1
+ );
+
+ fetch2_stall_in <= decode2_stall_out;
decode1_0: entity work.decode1
port map (
e_out => decode2_to_execute1,
l_out => decode2_to_loadstore1,
m_out => decode2_to_multiply,
+ d_out => decode2_to_divider,
r_in => register_file_to_decode2,
r_out => decode2_to_register_file,
c_in => cr_file_to_decode2,
);
register_file_0: entity work.register_file
+ generic map (
+ SIM => SIM
+ )
port map (
clk => clk,
d_in => decode2_to_register_file,
d_out => register_file_to_decode2,
w_in => writeback_to_register_file,
- registers_out => registers);
+ sim_dump => terminate
+ );
cr_file_0: entity work.cr_file
port map (
flush_out => flush,
e_in => decode2_to_execute1,
f_out => execute1_to_fetch1,
- e_out => execute1_to_execute2,
+ e_out => execute1_to_writeback,
terminate_out => terminate
);
- execute2_0: entity work.execute2
- port map (
- clk => clk,
- e_in => execute1_to_execute2,
- e_out => execute2_to_writeback
- );
-
loadstore1_0: entity work.loadstore1
port map (
clk => clk,
m_out => multiply_to_writeback
);
+ divider_0: entity work.divider
+ port map (
+ clk => clk,
+ rst => core_rst,
+ d_in => decode2_to_divider,
+ d_out => divider_to_writeback
+ );
+
writeback_0: entity work.writeback
port map (
clk => clk,
- e_in => execute2_to_writeback,
+ e_in => execute1_to_writeback,
l_in => loadstore2_to_writeback,
m_in => multiply_to_writeback,
+ d_in => divider_to_writeback,
w_out => writeback_to_register_file,
c_out => writeback_to_cr_file,
complete_out => complete
icache_rst => dbg_icache_rst,
terminate => terminate,
core_stopped => dbg_core_is_stopped,
- nia => fetch1_to_fetch2.nia,
+ nia => fetch1_to_icache.nia,
terminated_out => terminated_out
);
- -- Dump registers if core terminates
- sim_terminate_test: if SIM generate
- dump_registers: process(all)
- begin
- if terminate = '1' then
- loop_0: for i in 0 to 31 loop
- report "REG " & to_hstring(registers(i));
- end loop loop_0;
- assert false report "end of test" severity failure;
- end if;
- end process;
- end generate;
-
end behave;
projects / microwatt.git / blobdiff