Merge pull request #134 from paulusmack/master

[microwatt.git] / core.vhdl

diff --git a/core.vhdl b/core.vhdl
index 77af8824f371d15f31506ce908c52e40eafc0edb..bc0b16fecaefd93d06a7161f0496bb70e3ce47bf 100644 (file)
--- a/core.vhdl
+++ b/core.vhdl
@@ -8,7 +8,9 @@ use work.wishbone_types.all;
 
 entity core is
     generic (
-        SIM : boolean := false
+        SIM : boolean := false;
+       DISABLE_FLATTEN : boolean := false;
+        EX1_BYPASS : boolean := true
         );
     port (
         clk          : in std_logic;
@@ -58,24 +60,19 @@ architecture behave of core is
     signal execute1_to_fetch1: Execute1ToFetch1Type;
 
     -- load store signals
-    signal decode2_to_loadstore1: Decode2ToLoadstore1Type;
+    signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
     signal dcache_to_writeback: DcacheToWritebackType;
 
-    -- multiply signals
-    signal decode2_to_multiply: Decode2ToMultiplyType;
-    signal multiply_to_writeback: MultiplyToWritebackType;
-
-    -- divider signals
-    signal decode2_to_divider: Decode2ToDividerType;
-    signal divider_to_writeback: DividerToWritebackType;
-
     -- local signals
     signal fetch1_stall_in : std_ulogic;
     signal icache_stall_out : std_ulogic;
     signal fetch2_stall_in : std_ulogic;
     signal decode1_stall_in : std_ulogic;
+    signal decode2_stall_in : std_ulogic;
     signal decode2_stall_out : std_ulogic;
+    signal ex1_icache_inval: std_ulogic;
+    signal ex1_stall_out: std_ulogic;
 
     signal flush: std_ulogic;
 
@@ -84,6 +81,8 @@ architecture behave of core is
     signal core_rst: std_ulogic;
     signal icache_rst: std_ulogic;
 
+    signal sim_cr_dump: std_ulogic;
+
     -- Debug actions
     signal dbg_core_stop: std_ulogic;
     signal dbg_core_rst: std_ulogic;
@@ -92,6 +91,27 @@ architecture behave of core is
     -- Debug status
     signal dbg_core_is_stopped: std_ulogic;
 
+    function keep_h(disable : boolean) return string is
+    begin
+       if disable then
+           return "yes";
+       else
+           return "no";
+       end if;
+    end function;
+    attribute keep_hierarchy : string;
+    attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
+    attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
+    attribute keep_hierarchy of fetch2_0 : label is keep_h(DISABLE_FLATTEN);
+    attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
+    attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
+    attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
+    attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
+    attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
+    attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
+    attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
+    attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
+    attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 begin
 
     core_rst <= dbg_core_rst or rst;
@@ -114,6 +134,7 @@ begin
 
     icache_0: entity work.icache
         generic map(
+            SIM => SIM,
             LINE_SIZE => 64,
             NUM_LINES => 32,
            NUM_WAYS => 2
@@ -129,7 +150,7 @@ begin
             wishbone_in => wishbone_insn_in
             );
 
-    icache_rst <= rst or dbg_icache_rst;
+    icache_rst <= rst or dbg_icache_rst or ex1_icache_inval;
 
     fetch2_0: entity work.fetch2
         port map (
@@ -156,23 +177,25 @@ begin
     decode1_stall_in <= decode2_stall_out;
 
     decode2_0: entity work.decode2
+        generic map (
+            EX1_BYPASS => EX1_BYPASS
+            )
         port map (
             clk => clk,
             rst => core_rst,
+           stall_in => decode2_stall_in,
             stall_out => decode2_stall_out,
             flush_in => flush,
             complete_in => complete,
            stopped_out => dbg_core_is_stopped,
             d_in => decode1_to_decode2,
             e_out => decode2_to_execute1,
-            l_out => decode2_to_loadstore1,
-            m_out => decode2_to_multiply,
-            d_out => decode2_to_divider,
             r_in => register_file_to_decode2,
             r_out => decode2_to_register_file,
             c_in => cr_file_to_decode2,
             c_out => decode2_to_cr_file
             );
+    decode2_stall_in <= ex1_stall_out;
 
     register_file_0: entity work.register_file
         generic map (
@@ -183,34 +206,43 @@ begin
             d_in => decode2_to_register_file,
             d_out => register_file_to_decode2,
             w_in => writeback_to_register_file,
-           sim_dump => terminate
+           sim_dump => terminate,
+           sim_dump_done => sim_cr_dump
            );
 
     cr_file_0: entity work.cr_file
+        generic map (
+            SIM => SIM
+            )
         port map (
             clk => clk,
             d_in => decode2_to_cr_file,
             d_out => cr_file_to_decode2,
-            w_in => writeback_to_cr_file
+            w_in => writeback_to_cr_file,
+            sim_dump => sim_cr_dump
             );
 
     execute1_0: entity work.execute1
         generic map (
-            SIM => SIM
+            EX1_BYPASS => EX1_BYPASS
             )
         port map (
             clk => clk,
+            rst => core_rst,
             flush_out => flush,
+           stall_out => ex1_stall_out,
             e_in => decode2_to_execute1,
+            l_out => execute1_to_loadstore1,
             f_out => execute1_to_fetch1,
             e_out => execute1_to_writeback,
+           icache_inval => ex1_icache_inval,
             terminate_out => terminate
             );
 
     loadstore1_0: entity work.loadstore1
         port map (
             clk => clk,
-            l_in => decode2_to_loadstore1,
+            l_in => execute1_to_loadstore1,
             l_out => loadstore1_to_dcache
             );
 
@@ -229,28 +261,11 @@ begin
             wishbone_out => wishbone_data_out
             );
 
-    multiply_0: entity work.multiply
-        port map (
-            clk => clk,
-            m_in => decode2_to_multiply,
-            m_out => multiply_to_writeback
-            );
-
-    divider_0: entity work.divider
-        port map (
-            clk => clk,
-            rst => core_rst,
-            d_in => decode2_to_divider,
-            d_out => divider_to_writeback
-            );
-
     writeback_0: entity work.writeback
         port map (
             clk => clk,
             e_in => execute1_to_writeback,
             l_in => dcache_to_writeback,
-            m_in => multiply_to_writeback,
-            d_in => divider_to_writeback,
             w_out => writeback_to_register_file,
             c_out => writeback_to_cr_file,
             complete_out => complete