sim_console: Fix polling to check for POLLIN

[microwatt.git] / core_dram_tb.vhdl

diff --git a/core_dram_tb.vhdl b/core_dram_tb.vhdl
index d72b1e794ada194e7b1b7a389791f20af3973b7a..d0890cba87bcbb3c0b6b23e4bfac6aad4a651f17 100644 (file)
--- a/core_dram_tb.vhdl
+++ b/core_dram_tb.vhdl
@@ -26,10 +26,10 @@ architecture behave of core_dram_tb is
     -- Sim DRAM
     signal wb_dram_in : wishbone_master_out;
     signal wb_dram_out : wishbone_slave_out;
-    signal wb_dram_ctrl_in : wb_io_master_out;
-    signal wb_dram_ctrl_out : wb_io_slave_out;
-    signal wb_dram_is_csr   : std_ulogic;
-    signal wb_dram_is_init  : std_ulogic;
+    signal wb_ext_io_in : wb_io_master_out;
+    signal wb_ext_io_out : wb_io_slave_out;
+    signal wb_ext_is_dram_csr : std_ulogic;
+    signal wb_ext_is_dram_init : std_ulogic;
     signal core_alt_reset : std_ulogic;
 
     -- SPI
@@ -61,7 +61,6 @@ begin
            SIM => true,
            MEMORY_SIZE => MEMORY_SIZE,
            RAM_INIT_FILE => MAIN_RAM_FILE,
-           RESET_LOW => false,
             HAS_DRAM => true,
            DRAM_SIZE => 256 * 1024 * 1024,
             DRAM_INIT_SIZE => ROM_SIZE,
@@ -73,14 +72,12 @@ begin
        port map(
            rst => soc_rst,
            system_clk => system_clk,
-           uart0_rxd => '0',
-           uart0_txd => open,
            wb_dram_in => wb_dram_in,
            wb_dram_out => wb_dram_out,
-           wb_dram_ctrl_in => wb_dram_ctrl_in,
-           wb_dram_ctrl_out => wb_dram_ctrl_out,
-            wb_dram_is_csr => wb_dram_is_csr,
-            wb_dram_is_init => wb_dram_is_init,
+           wb_ext_io_in => wb_ext_io_in,
+           wb_ext_io_out => wb_ext_io_out,
+            wb_ext_is_dram_csr => wb_ext_is_dram_csr,
+            wb_ext_is_dram_init => wb_ext_is_dram_init,
             spi_flash_sck     => spi_sck,
             spi_flash_cs_n    => spi_cs_n,
             spi_flash_sdat_o  => spi_sdat_o,
@@ -127,38 +124,18 @@ begin
             PAYLOAD_SIZE => ROM_SIZE
             )
         port map(
-            clk_in             => clk,
+            clk_in          => clk,
             rst             => rst,
-            system_clk => system_clk,
-            system_reset       => soc_rst,
-            core_alt_reset     => core_alt_reset,
-            pll_locked => open,
-
-            wb_in              => wb_dram_in,
-            wb_out             => wb_dram_out,
-            wb_ctrl_in => wb_dram_ctrl_in,
-            wb_ctrl_out        => wb_dram_ctrl_out,
-            wb_ctrl_is_csr  => wb_dram_is_csr,
-            wb_ctrl_is_init => wb_dram_is_init,
-
-            init_done  => open,
-            init_error => open,
-
-            ddram_a            => open,
-            ddram_ba   => open,
-            ddram_ras_n        => open,
-            ddram_cas_n        => open,
-            ddram_we_n => open,
-            ddram_cs_n => open,
-            ddram_dm   => open,
-            ddram_dq   => open,
-            ddram_dqs_p        => open,
-            ddram_dqs_n        => open,
-            ddram_clk_p        => open,
-            ddram_clk_n        => open,
-            ddram_cke  => open,
-            ddram_odt  => open,
-            ddram_reset_n      => open
+            system_clk      => system_clk,
+            system_reset    => soc_rst,
+            core_alt_reset  => core_alt_reset,
+
+            wb_in           => wb_dram_in,
+            wb_out          => wb_dram_out,
+            wb_ctrl_in      => wb_ext_io_in,
+            wb_ctrl_out     => wb_ext_io_out,
+            wb_ctrl_is_csr  => wb_ext_is_dram_csr,
+            wb_ctrl_is_init => wb_ext_is_dram_init
             );
 
     clk_process: process