soc0: entity work.soc
generic map(
SIM => true,
- MEMORY_SIZE => 524288,
- RAM_INIT_FILE => "simple_ram_behavioural.bin",
- RESET_LOW => false
+ MEMORY_SIZE => (384*1024),
+ RAM_INIT_FILE => "main_ram.bin",
+ CLK_FREQ => 100000000
)
port map(
rst => rst,
- system_clk => clk,
- uart0_rxd => '0',
- uart0_txd => open
+ system_clk => clk
);
clk_process: process
end process;
jtag: entity work.sim_jtag;
+
end;